1 ; RUN: llc -march=mipsel < %s | FileCheck %s 2 ; RUN: llc -march=mipsel -force-mips-long-branch -O3 < %s \ 3 ; RUN: | FileCheck %s -check-prefix=O32 4 ; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -force-mips-long-branch -O3 \ 5 ; RUN: < %s | FileCheck %s -check-prefix=N64 6 ; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -force-mips-long-branch -O3 \ 7 ; RUN: < %s | FileCheck %s -check-prefix=N64 8 ; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=micromips \ 9 ; RUN: -force-mips-long-branch -O3 < %s | FileCheck %s -check-prefix=MICROMIPS 10 ; RUN: llc -mtriple=mipsel-none-nacl -force-mips-long-branch -O3 < %s \ 11 ; RUN: | FileCheck %s -check-prefix=NACL 12 13 14 @x = external global i32 15 16 define void @test1(i32 signext %s) { 17 entry: 18 %cmp = icmp eq i32 %s, 0 19 br i1 %cmp, label %end, label %then 20 21 then: 22 store i32 1, i32* @x, align 4 23 br label %end 24 25 end: 26 ret void 27 28 29 ; First check the normal version (without long branch). beqz jumps to return, 30 ; and fallthrough block stores 1 to global variable. 31 32 ; CHECK: lui $[[R0:[0-9]+]], %hi(_gp_disp) 33 ; CHECK: addiu $[[R0]], $[[R0]], %lo(_gp_disp) 34 ; CHECK: beqz $4, $[[BB0:BB[0-9_]+]] 35 ; CHECK: addu $[[GP:[0-9]+]], $[[R0]], $25 36 ; CHECK: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) 37 ; CHECK: addiu $[[R2:[0-9]+]], $zero, 1 38 ; CHECK: sw $[[R2]], 0($[[R1]]) 39 ; CHECK: $[[BB0]]: 40 ; CHECK: jr $ra 41 ; CHECK: nop 42 43 44 ; Check the MIPS32 version. Check that branch logic is inverted, so that the 45 ; target of the new branch (bnez) is the fallthrough block of the original 46 ; branch. Check that fallthrough block of the new branch contains long branch 47 ; expansion which at the end indirectly jumps to the target of the original 48 ; branch. 49 50 ; O32: lui $[[R0:[0-9]+]], %hi(_gp_disp) 51 ; O32: addiu $[[R0]], $[[R0]], %lo(_gp_disp) 52 ; O32: bnez $4, $[[BB0:BB[0-9_]+]] 53 ; O32: addu $[[GP:[0-9]+]], $[[R0]], $25 54 55 ; Check for long branch expansion: 56 ; O32: addiu $sp, $sp, -8 57 ; O32-NEXT: sw $ra, 0($sp) 58 ; O32-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) 59 ; O32-NEXT: bal $[[BB1]] 60 ; O32-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) 61 ; O32-NEXT: $[[BB1]]: 62 ; O32-NEXT: addu $1, $ra, $1 63 ; O32-NEXT: lw $ra, 0($sp) 64 ; O32-NEXT: jr $1 65 ; O32-NEXT: addiu $sp, $sp, 8 66 67 ; O32: $[[BB0]]: 68 ; O32: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) 69 ; O32: addiu $[[R2:[0-9]+]], $zero, 1 70 ; O32: sw $[[R2]], 0($[[R1]]) 71 ; O32: $[[BB2]]: 72 ; O32: jr $ra 73 ; O32: nop 74 75 76 ; Check the MIPS64 version. 77 78 ; N64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test1))) 79 ; N64: bnez $4, $[[BB0:BB[0-9_]+]] 80 ; N64: daddu $[[R1:[0-9]+]], $[[R0]], $25 81 82 ; Check for long branch expansion: 83 ; N64: daddiu $sp, $sp, -16 84 ; N64-NEXT: sd $ra, 0($sp) 85 ; N64-NEXT: daddiu $1, $zero, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) 86 ; N64-NEXT: dsll $1, $1, 16 87 ; N64-NEXT: bal $[[BB1]] 88 ; N64-NEXT: daddiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) 89 ; N64-NEXT: $[[BB1]]: 90 ; N64-NEXT: daddu $1, $ra, $1 91 ; N64-NEXT: ld $ra, 0($sp) 92 ; N64-NEXT: jr $1 93 ; N64-NEXT: daddiu $sp, $sp, 16 94 95 ; N64: $[[BB0]]: 96 ; N64: daddiu $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1))) 97 ; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]]) 98 ; N64: addiu $[[R3:[0-9]+]], $zero, 1 99 ; N64: sw $[[R3]], 0($[[R2]]) 100 ; N64: $[[BB2]]: 101 ; N64: jr $ra 102 ; N64: nop 103 104 105 ; Check the microMIPS version. 106 107 ; MICROMIPS: lui $[[R0:[0-9]+]], %hi(_gp_disp) 108 ; MICROMIPS: addiu $[[R0]], $[[R0]], %lo(_gp_disp) 109 ; MICROMIPS: bnez $4, $[[BB0:BB[0-9_]+]] 110 ; MICROMIPS: addu $[[GP:[0-9]+]], $[[R0]], $25 111 112 ; Check for long branch expansion: 113 ; MICROMIPS: addiu $sp, $sp, -8 114 ; MICROMIPS-NEXT: sw $ra, 0($sp) 115 ; MICROMIPS-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) 116 ; MICROMIPS-NEXT: bal $[[BB1]] 117 ; MICROMIPS-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) 118 ; MICROMIPS-NEXT: $[[BB1]]: 119 ; MICROMIPS-NEXT: addu $1, $ra, $1 120 ; MICROMIPS-NEXT: lw $ra, 0($sp) 121 ; MICROMIPS-NEXT: jr $1 122 ; MICROMIPS-NEXT: addiu $sp, $sp, 8 123 124 ; MICROMIPS: $[[BB0]]: 125 ; MICROMIPS: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) 126 ; MICROMIPS: li16 $[[R2:[0-9]+]], 1 127 ; MICROMIPS: sw16 $[[R2]], 0($[[R1]]) 128 ; MICROMIPS: $[[BB2]]: 129 ; MICROMIPS: jrc $ra 130 131 132 ; Check the NaCl version. Check that sp change is not in the branch delay slot 133 ; of "jr $1" instruction. Check that target of indirect branch "jr $1" is 134 ; bundle aligned. 135 136 ; NACL: lui $[[R0:[0-9]+]], %hi(_gp_disp) 137 ; NACL: addiu $[[R0]], $[[R0]], %lo(_gp_disp) 138 ; NACL: bnez $4, $[[BB0:BB[0-9_]+]] 139 ; NACL: addu $[[GP:[0-9]+]], $[[R0]], $25 140 141 ; Check for long branch expansion: 142 ; NACL: addiu $sp, $sp, -8 143 ; NACL-NEXT: sw $ra, 0($sp) 144 ; NACL-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]])) 145 ; NACL-NEXT: bal $[[BB1]] 146 ; NACL-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]])) 147 ; NACL-NEXT: $[[BB1]]: 148 ; NACL-NEXT: addu $1, $ra, $1 149 ; NACL-NEXT: lw $ra, 0($sp) 150 ; NACL-NEXT: addiu $sp, $sp, 8 151 ; NACL-NEXT: jr $1 152 ; NACL-NEXT: nop 153 154 ; NACL: $[[BB0]]: 155 ; NACL: lw $[[R1:[0-9]+]], %got(x)($[[GP]]) 156 ; NACL: addiu $[[R2:[0-9]+]], $zero, 1 157 ; NACL: sw $[[R2]], 0($[[R1]]) 158 ; NACL: .align 4 159 ; NACL-NEXT: $[[BB2]]: 160 ; NACL: jr $ra 161 ; NACL: nop 162 } 163
