1 ; RUN: llc < %s -mcpu=pwr7 -mattr=-vsx| FileCheck %s 2 ; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s 3 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" 4 target triple = "powerpc64-unknown-linux-gnu" 5 6 define fastcc void @copy_to_conceal() #0 { 7 entry: 8 br i1 undef, label %if.then, label %if.end210 9 10 if.then: ; preds = %entry 11 br label %vector.body.i 12 13 vector.body.i: ; preds = %vector.body.i, %if.then 14 %index.i = phi i64 [ 0, %vector.body.i ], [ 0, %if.then ] 15 store <8 x i16> zeroinitializer, <8 x i16>* undef, align 2 16 br label %vector.body.i 17 18 if.end210: ; preds = %entry 19 ret void 20 21 ; This will generate two align-1 i64 stores. Make sure that they are 22 ; indexed stores and not in r+i form (which require the offset to be 23 ; a multiple of 4). 24 ; CHECK: @copy_to_conceal 25 ; CHECK: stdx {{[0-9]+}}, 0, 26 27 ; CHECK-VSX: @copy_to_conceal 28 ; CHECK-VSX: stxvw4x {{[0-9]+}}, 0, 29 } 30 31 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } 32
