1 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s 2 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ 3 ; RUN: --check-prefix=CHECK-BE 4 ; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \ 5 ; RUN: --check-prefix=CHECK-P7 6 7 ; Function Attrs: norecurse nounwind readnone 8 define signext i32 @geti(<4 x i32> %a, i32 signext %b) { 9 entry: 10 %vecext = extractelement <4 x i32> %a, i32 %b 11 ret i32 %vecext 12 ; CHECK-LABEL: @geti 13 ; CHECK-P7-LABEL: @geti 14 ; CHECK-BE-LABEL: @geti 15 ; CHECK-DAG: li [[TRUNCREG:[0-9]+]], 2 16 ; CHECK-DAG: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5 17 ; CHECK-DAG: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 2 18 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 19 ; CHECK-DAG: vperm [[PERMVEC:[0-9]+]], 2, 2, [[SHMSKREG]] 20 ; CHECK-DAG: li [[ONEREG:[0-9]+]], 1 21 ; CHECK-DAG: and [[ELEMSREG:[0-9]+]], [[ONEREG]], 5 22 ; CHECK-DAG: sldi [[SHAMREG:[0-9]+]], [[ELEMSREG]], 5 23 ; CHECK: mfvsrd [[TOGPR:[0-9]+]], 24 ; CHECK: srd [[RSHREG:[0-9]+]], [[TOGPR]], [[SHAMREG]] 25 ; CHECK: extsw 3, [[RSHREG]] 26 ; CHECK-P7-DAG: sldi [[ELEMOFFREG:[0-9]+]], 5, 2 27 ; CHECK-P7-DAG: stxvw4x 34, 28 ; CHECK-P7: lwax 3, [[ELEMOFFREG]], 29 ; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 2 30 ; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 2 31 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 32 ; CHECK-BE-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] 33 ; CHECK-BE-DAG: li [[IMMREG:[0-9]+]], 1 34 ; CHECK-BE-DAG: andc [[ANDCREG:[0-9]+]], [[IMMREG]], 5 35 ; CHECK-BE-DAG: sldi [[SHAMREG:[0-9]+]], [[ANDCREG]], 5 36 ; CHECK-BE: mfvsrd [[TOGPR:[0-9]+]], 37 ; CHECK-BE: srd [[RSHREG:[0-9]+]], [[TOGPR]], [[SHAMREG]] 38 ; CHECk-BE: extsw 3, [[RSHREG]] 39 } 40 41 ; Function Attrs: norecurse nounwind readnone 42 define i64 @getl(<2 x i64> %a, i32 signext %b) { 43 entry: 44 %vecext = extractelement <2 x i64> %a, i32 %b 45 ret i64 %vecext 46 ; CHECK-LABEL: @getl 47 ; CHECK-P7-LABEL: @getl 48 ; CHECK-BE-LABEL: @getl 49 ; CHECK-DAG: li [[TRUNCREG:[0-9]+]], 1 50 ; CHECK-DAG: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5 51 ; CHECK-DAG: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 3 52 ; CHECK-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 53 ; CHECK-DAG: vperm [[PERMVEC:[0-9]+]], 2, 2, [[SHMSKREG]] 54 ; CHECK: mfvsrd 3, 55 ; CHECK-P7-DAG: sldi [[ELEMOFFREG:[0-9]+]], 5, 3 56 ; CHECK-P7-DAG: stxvd2x 34, 57 ; CHECK-P7: ldx 3, [[ELEMOFFREG]], 58 ; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 1 59 ; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3 60 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 61 ; CHECK-BE-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] 62 ; CHECK-BE: mfvsrd 3, 63 } 64 65 ; Function Attrs: norecurse nounwind readnone 66 define float @getf(<4 x float> %a, i32 signext %b) { 67 entry: 68 %vecext = extractelement <4 x float> %a, i32 %b 69 ret float %vecext 70 ; CHECK-LABEL: @getf 71 ; CHECK-P7-LABEL: @getf 72 ; CHECK-BE-LABEL: @getf 73 ; CHECK: li [[IMMREG:[0-9]+]], 3 74 ; CHECK: xor [[TRUNCREG:[0-9]+]], [[IMMREG]], 5 75 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[TRUNCREG]] 76 ; CHECK: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] 77 ; CHECK: xscvspdpn 1, 78 ; CHECK-P7-DAG: sldi [[ELEMOFFREG:[0-9]+]], 5, 2 79 ; CHECK-P7-DAG: stxvw4x 34, 80 ; CHECK-P7: lfsx 1, [[ELEMOFFREG]], 81 ; CHECK-BE: sldi [[ELNOREG:[0-9]+]], 5, 2 82 ; CHECK-BE: lvsl [[SHMSKREG:[0-9]+]], 0, [[ELNOREG]] 83 ; CHECK-BE: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] 84 ; CHECK-BE: xscvspdpn 1, 85 } 86 87 ; Function Attrs: norecurse nounwind readnone 88 define double @getd(<2 x double> %a, i32 signext %b) { 89 entry: 90 %vecext = extractelement <2 x double> %a, i32 %b 91 ret double %vecext 92 ; CHECK-LABEL: @getd 93 ; CHECK-P7-LABEL: @getd 94 ; CHECK-BE-LABEL: @getd 95 ; CHECK: li [[TRUNCREG:[0-9]+]], 1 96 ; CHECK: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5 97 ; CHECK: sldi [[SHIFTREG:[0-9]+]], [[MASKREG]], 3 98 ; CHECK: lvsl [[SHMSKREG:[0-9]+]], 0, [[SHIFTREG]] 99 ; CHECK: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] 100 ; FIXME: the instruction below is a redundant regclass copy, to be removed 101 ; CHECK: xxlor 1, 102 ; CHECK-P7-DAG: andi. [[ANDREG:[0-9]+]], 5, 1 103 ; CHECK-P7-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3 104 ; CHECK-P7-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 105 ; CHECK-P7-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] 106 ; FIXME: the instruction below is a redundant regclass copy, to be removed 107 ; CHECK-P7: xxlor 1, 108 ; CHECK-BE-DAG: andi. [[ANDREG:[0-9]+]], 5, 1 109 ; CHECK-BE-DAG: sldi [[SLREG:[0-9]+]], [[ANDREG]], 3 110 ; CHECK-BE-DAG: lvsl [[SHMSKREG:[0-9]+]], 0, [[SLREG]] 111 ; CHECK-BE-DAG: vperm {{[0-9]+}}, 2, 2, [[SHMSKREG]] 112 ; FIXME: the instruction below is a redundant regclass copy, to be removed 113 ; CHECK-BE: xxlor 1, 114 } 115
