1 ; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck %s 2 ; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s 3 ; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s 4 ; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-unknown-linux-gnu -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s 5 ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-LE %s 6 7 define double @test1(double %a, double %b) { 8 entry: 9 %v = fmul double %a, %b 10 ret double %v 11 12 ; CHECK-LABEL: @test1 13 ; CHECK: xsmuldp 1, 1, 2 14 ; CHECK: blr 15 16 ; CHECK-LE-LABEL: @test1 17 ; CHECK-LE: xsmuldp 1, 1, 2 18 ; CHECK-LE: blr 19 } 20 21 define double @test2(double %a, double %b) { 22 entry: 23 %v = fdiv double %a, %b 24 ret double %v 25 26 ; CHECK-LABEL: @test2 27 ; CHECK: xsdivdp 1, 1, 2 28 ; CHECK: blr 29 30 ; CHECK-LE-LABEL: @test2 31 ; CHECK-LE: xsdivdp 1, 1, 2 32 ; CHECK-LE: blr 33 } 34 35 define double @test3(double %a, double %b) { 36 entry: 37 %v = fadd double %a, %b 38 ret double %v 39 40 ; CHECK-LABEL: @test3 41 ; CHECK: xsadddp 1, 1, 2 42 ; CHECK: blr 43 44 ; CHECK-LE-LABEL: @test3 45 ; CHECK-LE: xsadddp 1, 1, 2 46 ; CHECK-LE: blr 47 } 48 49 define <2 x double> @test4(<2 x double> %a, <2 x double> %b) { 50 entry: 51 %v = fadd <2 x double> %a, %b 52 ret <2 x double> %v 53 54 ; CHECK-LABEL: @test4 55 ; CHECK: xvadddp 34, 34, 35 56 ; CHECK: blr 57 58 ; CHECK-LE-LABEL: @test4 59 ; CHECK-LE: xvadddp 34, 34, 35 60 ; CHECK-LE: blr 61 } 62 63 define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) { 64 entry: 65 %v = xor <4 x i32> %a, %b 66 ret <4 x i32> %v 67 68 ; CHECK-REG-LABEL: @test5 69 ; CHECK-REG: xxlxor 34, 34, 35 70 ; CHECK-REG: blr 71 72 ; CHECK-FISL-LABEL: @test5 73 ; CHECK-FISL: vor 74 ; CHECK-FISL: vor 75 ; CHECK-FISL: xxlxor 76 ; CHECK-FISL: vor 2 77 ; CHECK-FISL: blr 78 79 ; CHECK-LE-LABEL: @test5 80 ; CHECK-LE: xxlxor 34, 34, 35 81 ; CHECK-LE: blr 82 } 83 84 define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) { 85 entry: 86 %v = xor <8 x i16> %a, %b 87 ret <8 x i16> %v 88 89 ; CHECK-REG-LABEL: @test6 90 ; CHECK-REG: xxlxor 34, 34, 35 91 ; CHECK-REG: blr 92 93 ; CHECK-FISL-LABEL: @test6 94 ; CHECK-FISL: vor 4, 2, 2 95 ; CHECK-FISL: vor 5, 3, 3 96 ; CHECK-FISL: xxlxor 36, 36, 37 97 ; CHECK-FISL: vor 2, 4, 4 98 ; CHECK-FISL: blr 99 100 ; CHECK-LE-LABEL: @test6 101 ; CHECK-LE: xxlxor 34, 34, 35 102 ; CHECK-LE: blr 103 } 104 105 define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) { 106 entry: 107 %v = xor <16 x i8> %a, %b 108 ret <16 x i8> %v 109 110 ; CHECK-REG-LABEL: @test7 111 ; CHECK-REG: xxlxor 34, 34, 35 112 ; CHECK-REG: blr 113 114 ; CHECK-FISL-LABEL: @test7 115 ; CHECK-FISL: vor 4, 2, 2 116 ; CHECK-FISL: vor 5, 3, 3 117 ; CHECK-FISL: xxlxor 36, 36, 37 118 ; CHECK-FISL: vor 2, 4, 4 119 ; CHECK-FISL: blr 120 121 ; CHECK-LE-LABEL: @test7 122 ; CHECK-LE: xxlxor 34, 34, 35 123 ; CHECK-LE: blr 124 } 125 126 define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) { 127 entry: 128 %v = or <4 x i32> %a, %b 129 ret <4 x i32> %v 130 131 ; CHECK-REG-LABEL: @test8 132 ; CHECK-REG: xxlor 34, 34, 35 133 ; CHECK-REG: blr 134 135 ; CHECK-FISL-LABEL: @test8 136 ; CHECK-FISL: vor 137 ; CHECK-FISL: vor 138 ; CHECK-FISL: xxlor 139 ; CHECK-FISL: vor 2 140 ; CHECK-FISL: blr 141 142 ; CHECK-LE-LABEL: @test8 143 ; CHECK-LE: xxlor 34, 34, 35 144 ; CHECK-LE: blr 145 } 146 147 define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) { 148 entry: 149 %v = or <8 x i16> %a, %b 150 ret <8 x i16> %v 151 152 ; CHECK-REG-LABEL: @test9 153 ; CHECK-REG: xxlor 34, 34, 35 154 ; CHECK-REG: blr 155 156 ; CHECK-FISL-LABEL: @test9 157 ; CHECK-FISL: vor 4, 2, 2 158 ; CHECK-FISL: vor 5, 3, 3 159 ; CHECK-FISL: xxlor 36, 36, 37 160 ; CHECK-FISL: vor 2, 4, 4 161 ; CHECK-FISL: blr 162 163 ; CHECK-LE-LABEL: @test9 164 ; CHECK-LE: xxlor 34, 34, 35 165 ; CHECK-LE: blr 166 } 167 168 define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) { 169 entry: 170 %v = or <16 x i8> %a, %b 171 ret <16 x i8> %v 172 173 ; CHECK-REG-LABEL: @test10 174 ; CHECK-REG: xxlor 34, 34, 35 175 ; CHECK-REG: blr 176 177 ; CHECK-FISL-LABEL: @test10 178 ; CHECK-FISL: vor 4, 2, 2 179 ; CHECK-FISL: vor 5, 3, 3 180 ; CHECK-FISL: xxlor 36, 36, 37 181 ; CHECK-FISL: vor 2, 4, 4 182 ; CHECK-FISL: blr 183 184 ; CHECK-LE-LABEL: @test10 185 ; CHECK-LE: xxlor 34, 34, 35 186 ; CHECK-LE: blr 187 } 188 189 define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) { 190 entry: 191 %v = and <4 x i32> %a, %b 192 ret <4 x i32> %v 193 194 ; CHECK-REG-LABEL: @test11 195 ; CHECK-REG: xxland 34, 34, 35 196 ; CHECK-REG: blr 197 198 ; CHECK-FISL-LABEL: @test11 199 ; CHECK-FISL: vor 200 ; CHECK-FISL: vor 201 ; CHECK-FISL: xxland 202 ; CHECK-FISL: vor 2 203 ; CHECK-FISL: blr 204 205 ; CHECK-LE-LABEL: @test11 206 ; CHECK-LE: xxland 34, 34, 35 207 ; CHECK-LE: blr 208 } 209 210 define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) { 211 entry: 212 %v = and <8 x i16> %a, %b 213 ret <8 x i16> %v 214 215 ; CHECK-REG-LABEL: @test12 216 ; CHECK-REG: xxland 34, 34, 35 217 ; CHECK-REG: blr 218 219 ; CHECK-FISL-LABEL: @test12 220 ; CHECK-FISL: vor 4, 2, 2 221 ; CHECK-FISL: vor 5, 3, 3 222 ; CHECK-FISL: xxland 36, 36, 37 223 ; CHECK-FISL: vor 2, 4, 4 224 ; CHECK-FISL: blr 225 226 ; CHECK-LE-LABEL: @test12 227 ; CHECK-LE: xxland 34, 34, 35 228 ; CHECK-LE: blr 229 } 230 231 define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) { 232 entry: 233 %v = and <16 x i8> %a, %b 234 ret <16 x i8> %v 235 236 ; CHECK-REG-LABEL: @test13 237 ; CHECK-REG: xxland 34, 34, 35 238 ; CHECK-REG: blr 239 240 ; CHECK-FISL-LABEL: @test13 241 ; CHECK-FISL: vor 4, 2, 2 242 ; CHECK-FISL: vor 5, 3, 3 243 ; CHECK-FISL: xxland 36, 36, 37 244 ; CHECK-FISL: vor 2, 4, 4 245 ; CHECK-FISL: blr 246 247 ; CHECK-LE-LABEL: @test13 248 ; CHECK-LE: xxland 34, 34, 35 249 ; CHECK-LE: blr 250 } 251 252 define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) { 253 entry: 254 %v = or <4 x i32> %a, %b 255 %w = xor <4 x i32> %v, <i32 -1, i32 -1, i32 -1, i32 -1> 256 ret <4 x i32> %w 257 258 ; CHECK-REG-LABEL: @test14 259 ; CHECK-REG: xxlnor 34, 34, 35 260 ; CHECK-REG: blr 261 262 ; CHECK-FISL-LABEL: @test14 263 ; CHECK-FISL: vor 4, 3, 3 264 ; CHECK-FISL: vor 5, 2, 2 265 ; CHECK-FISL: xxlor 0, 37, 36 266 ; CHECK-FISL: xxlnor 36, 37, 36 267 ; CHECK-FISL: vor 2, 4, 4 268 ; CHECK-FISL: lis 0, -1 269 ; CHECK-FISL: ori 0, 0, 65520 270 ; CHECK-FISL: stxvd2x 0, 1, 0 271 ; CHECK-FISL: blr 272 273 ; CHECK-LE-LABEL: @test14 274 ; CHECK-LE: xxlnor 34, 34, 35 275 ; CHECK-LE: blr 276 } 277 278 define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) { 279 entry: 280 %v = or <8 x i16> %a, %b 281 %w = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 282 ret <8 x i16> %w 283 284 ; CHECK-REG-LABEL: @test15 285 ; CHECK-REG: xxlnor 34, 34, 35 286 ; CHECK-REG: blr 287 288 ; CHECK-FISL-LABEL: @test15 289 ; CHECK-FISL: vor 4, 2, 2 290 ; CHECK-FISL: vor 5, 3, 3 291 ; CHECK-FISL: xxlor 36, 36, 37 292 ; CHECK-FISL: vor 0, 4, 4 293 ; CHECK-FISL: vor 4, 2, 2 294 ; CHECK-FISL: vor 5, 3, 3 295 ; CHECK-FISL: xxlnor 36, 36, 37 296 ; CHECK-FISL: vor 2, 4, 4 297 ; CHECK-FISL: lis 0, -1 298 ; CHECK-FISL: ori 0, 0, 65520 299 ; CHECK-FISL: stvx 0, 1, 0 300 ; CHECK-FISL: blr 301 302 ; CHECK-LE-LABEL: @test15 303 ; CHECK-LE: xxlnor 34, 34, 35 304 ; CHECK-LE: blr 305 } 306 307 define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) { 308 entry: 309 %v = or <16 x i8> %a, %b 310 %w = xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 311 ret <16 x i8> %w 312 313 ; CHECK-REG-LABEL: @test16 314 ; CHECK-REG: xxlnor 34, 34, 35 315 ; CHECK-REG: blr 316 317 ; CHECK-FISL-LABEL: @test16 318 ; CHECK-FISL: vor 4, 2, 2 319 ; CHECK-FISL: vor 5, 3, 3 320 ; CHECK-FISL: xxlor 36, 36, 37 321 ; CHECK-FISL: vor 0, 4, 4 322 ; CHECK-FISL: vor 4, 2, 2 323 ; CHECK-FISL: vor 5, 3, 3 324 ; CHECK-FISL: xxlnor 36, 36, 37 325 ; CHECK-FISL: vor 2, 4, 4 326 ; CHECK-FISL: lis 0, -1 327 ; CHECK-FISL: ori 0, 0, 65520 328 ; CHECK-FISL: stvx 0, 1, 0 329 ; CHECK-FISL: blr 330 331 ; CHECK-LE-LABEL: @test16 332 ; CHECK-LE: xxlnor 34, 34, 35 333 ; CHECK-LE: blr 334 } 335 336 define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) { 337 entry: 338 %w = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1> 339 %v = and <4 x i32> %a, %w 340 ret <4 x i32> %v 341 342 ; CHECK-REG-LABEL: @test17 343 ; CHECK-REG: xxlandc 34, 34, 35 344 ; CHECK-REG: blr 345 346 ; CHECK-FISL-LABEL: @test17 347 ; CHECK-FISL: vor 4, 3, 3 348 ; CHECK-FISL: vor 5, 2, 2 349 ; CHECK-FISL: vspltisb 2, -1 350 ; CHECK-FISL: vor 0, 2, 2 351 ; CHECK-FISL: xxlxor 36, 36, 32 352 ; CHECK-FISL: xxland 36, 37, 36 353 ; CHECK-FISL: vor 2, 4, 4 354 ; CHECK-FISL: blr 355 356 ; CHECK-LE-LABEL: @test17 357 ; CHECK-LE: xxlandc 34, 34, 35 358 ; CHECK-LE: blr 359 } 360 361 define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) { 362 entry: 363 %w = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 364 %v = and <8 x i16> %a, %w 365 ret <8 x i16> %v 366 367 ; CHECK-REG-LABEL: @test18 368 ; CHECK-REG: xxlandc 34, 34, 35 369 ; CHECK-REG: blr 370 371 ; CHECK-FISL-LABEL: @test18 372 ; CHECK-FISL: vspltisb 4, -1 373 ; CHECK-FISL: vor 5, 3, 3 374 ; CHECK-FISL: vor 0, 4, 4 375 ; CHECK-FISL: xxlxor 37, 37, 32 376 ; CHECK-FISL: vor 4, 5, 5 377 ; CHECK-FISL: vor 5, 2, 2 378 ; CHECK-FISL: vor 0, 3, 3 379 ; CHECK-FISL: xxlandc 37, 37, 32 380 ; CHECK-FISL: vor 2, 5, 5 381 ; CHECK-FISL: lis 0, -1 382 ; CHECK-FISL: ori 0, 0, 65520 383 ; CHECK-FISL: stvx 4, 1, 0 384 ; CHECK-FISL: blr 385 386 ; CHECK-LE-LABEL: @test18 387 ; CHECK-LE: xxlandc 34, 34, 35 388 ; CHECK-LE: blr 389 } 390 391 define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) { 392 entry: 393 %w = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> 394 %v = and <16 x i8> %a, %w 395 ret <16 x i8> %v 396 397 ; CHECK-REG-LABEL: @test19 398 ; CHECK-REG: xxlandc 34, 34, 35 399 ; CHECK-REG: blr 400 401 ; CHECK-FISL-LABEL: @test19 402 ; CHECK-FISL: vspltisb 4, -1 403 ; CHECK-FISL: vor 5, 3, 3 404 ; CHECK-FISL: vor 0, 4, 4 405 ; CHECK-FISL: xxlxor 37, 37, 32 406 ; CHECK-FISL: vor 4, 5, 5 407 ; CHECK-FISL: vor 5, 2, 2 408 ; CHECK-FISL: vor 0, 3, 3 409 ; CHECK-FISL: xxlandc 37, 37, 32 410 ; CHECK-FISL: vor 2, 5, 5 411 ; CHECK-FISL: lis 0, -1 412 ; CHECK-FISL: ori 0, 0, 65520 413 ; CHECK-FISL: stvx 4, 1, 0 414 ; CHECK-FISL: blr 415 416 ; CHECK-LE-LABEL: @test19 417 ; CHECK-LE: xxlandc 34, 34, 35 418 ; CHECK-LE: blr 419 } 420 421 define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) { 422 entry: 423 %m = icmp eq <4 x i32> %c, %d 424 %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b 425 ret <4 x i32> %v 426 427 ; CHECK-REG-LABEL: @test20 428 ; CHECK-REG: vcmpequw {{[0-9]+}}, 4, 5 429 ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} 430 ; CHECK-REG: blr 431 432 ; FIXME: The fast-isel code is pretty miserable for this one. 433 434 ; CHECK-FISL-LABEL: @test20 435 ; CHECK-FISL: vor 0, 5, 5 436 ; CHECK-FISL: vor 1, 4, 4 437 ; CHECK-FISL: vor 6, 3, 3 438 ; CHECK-FISL: vor 7, 2, 2 439 ; CHECK-FISL: vor 2, 1, 1 440 ; CHECK-FISL: vor 3, 0, 0 441 ; CHECK-FISL: vcmpequw 2, 2, 3 442 ; CHECK-FISL: vor 0, 2, 2 443 ; CHECK-FISL: xxsel 32, 38, 39, 32 444 ; CHECK-FISL: vor 2, 0, 0 445 ; CHECK-FISL: blr 446 447 ; CHECK-LE-LABEL: @test20 448 ; CHECK-LE: vcmpequw {{[0-9]+}}, 4, 5 449 ; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}} 450 ; CHECK-LE: blr 451 } 452 453 define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) { 454 entry: 455 %m = fcmp oeq <4 x float> %c, %d 456 %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b 457 ret <4 x float> %v 458 459 ; CHECK-REG-LABEL: @test21 460 ; CHECK-REG: xvcmpeqsp [[V1:[0-9]+]], 36, 37 461 ; CHECK-REG: xxsel 34, 35, 34, [[V1]] 462 ; CHECK-REG: blr 463 464 ; CHECK-FISL-LABEL: @test21 465 ; CHECK-FISL: vor 0, 5, 5 466 ; CHECK-FISL: vor 1, 4, 4 467 ; CHECK-FISL: vor 6, 3, 3 468 ; CHECK-FISL: vor 7, 2, 2 469 ; CHECK-FISL: xvcmpeqsp 32, 33, 32 470 ; CHECK-FISL: xxsel 32, 38, 39, 32 471 ; CHECK-FISL: vor 2, 0, 0 472 ; CHECK-FISL: blr 473 474 ; CHECK-LE-LABEL: @test21 475 ; CHECK-LE: xvcmpeqsp [[V1:[0-9]+]], 36, 37 476 ; CHECK-LE: xxsel 34, 35, 34, [[V1]] 477 ; CHECK-LE: blr 478 } 479 480 define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) { 481 entry: 482 %m = fcmp ueq <4 x float> %c, %d 483 %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b 484 ret <4 x float> %v 485 486 ; CHECK-REG-LABEL: @test22 487 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37 488 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36 489 ; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37 490 ; CHECK-REG-DAG: xxlnor 491 ; CHECK-REG-DAG: xxlnor 492 ; CHECK-REG-DAG: xxlor 493 ; CHECK-REG-DAG: xxlor 494 ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} 495 ; CHECK-REG: blr 496 497 ; CHECK-FISL-LABEL: @test22 498 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 33, 32 499 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 32, 32 500 ; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 33, 33 501 ; CHECK-FISL-DAG: xxlnor 502 ; CHECK-FISL-DAG: xxlnor 503 ; CHECK-FISL-DAG: xxlor 504 ; CHECK-FISL-DAG: xxlor 505 ; CHECK-FISL: xxsel 0, 38, 39, {{[0-9]+}} 506 ; CHECK-FISL: blr 507 508 ; CHECK-LE-LABEL: @test22 509 ; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37 510 ; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36 511 ; CHECK-LE-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37 512 ; CHECK-LE-DAG: xxlnor 513 ; CHECK-LE-DAG: xxlnor 514 ; CHECK-LE-DAG: xxlor 515 ; CHECK-LE-DAG: xxlor 516 ; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}} 517 ; CHECK-LE: blr 518 } 519 520 define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) { 521 entry: 522 %m = icmp eq <8 x i16> %c, %d 523 %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b 524 ret <8 x i16> %v 525 526 ; CHECK-REG-LABEL: @test23 527 ; CHECK-REG: vcmpequh {{[0-9]+}}, 4, 5 528 ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} 529 ; CHECK-REG: blr 530 531 ; CHECK-FISL-LABEL: @test23 532 ; CHECK-FISL: vcmpequh 4, 4, 5 533 ; CHECK-FISL: vor 0, 3, 3 534 ; CHECK-FISL: vor 1, 2, 2 535 ; CHECK-FISL: vor 6, 4, 4 536 ; CHECK-FISL: xxsel 32, 32, 33, 38 537 ; CHECK-FISL: vor 2, 0, 538 ; CHECK-FISL: blr 539 540 ; CHECK-LE-LABEL: @test23 541 ; CHECK-LE: vcmpequh {{[0-9]+}}, 4, 5 542 ; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}} 543 ; CHECK-LE: blr 544 } 545 546 define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) { 547 entry: 548 %m = icmp eq <16 x i8> %c, %d 549 %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b 550 ret <16 x i8> %v 551 552 ; CHECK-REG-LABEL: @test24 553 ; CHECK-REG: vcmpequb {{[0-9]+}}, 4, 5 554 ; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} 555 ; CHECK-REG: blr 556 557 ; CHECK-FISL-LABEL: @test24 558 ; CHECK-FISL: vcmpequb 4, 4, 5 559 ; CHECK-FISL: vor 0, 3, 3 560 ; CHECK-FISL: vor 1, 2, 2 561 ; CHECK-FISL: vor 6, 4, 4 562 ; CHECK-FISL: xxsel 32, 32, 33, 38 563 ; CHECK-FISL: vor 2, 0, 0 564 ; CHECK-FISL: blr 565 566 ; CHECK-LE-LABEL: @test24 567 ; CHECK-LE: vcmpequb {{[0-9]+}}, 4, 5 568 ; CHECK-LE: xxsel 34, 35, 34, {{[0-9]+}} 569 ; CHECK-LE: blr 570 } 571 572 define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) { 573 entry: 574 %m = fcmp oeq <2 x double> %c, %d 575 %v = select <2 x i1> %m, <2 x double> %a, <2 x double> %b 576 ret <2 x double> %v 577 578 ; CHECK-LABEL: @test25 579 ; CHECK: xvcmpeqdp [[V1:[0-9]+]], 36, 37 580 ; CHECK: xxsel 34, 35, 34, [[V1]] 581 ; CHECK: blr 582 583 ; CHECK-LE-LABEL: @test25 584 ; CHECK-LE: xvcmpeqdp [[V1:[0-9]+]], 36, 37 585 ; CHECK-LE: xxsel 34, 35, 34, [[V1]] 586 ; CHECK-LE: blr 587 } 588 589 define <2 x i64> @test26(<2 x i64> %a, <2 x i64> %b) { 590 %v = add <2 x i64> %a, %b 591 ret <2 x i64> %v 592 593 ; CHECK-LABEL: @test26 594 595 ; Make sure we use only two stores (one for each operand). 596 ; CHECK: stxvd2x 35, 597 ; CHECK: stxvd2x 34, 598 ; CHECK-NOT: stxvd2x 599 600 ; FIXME: The code quality here is not good; just make sure we do something for now. 601 ; CHECK: add 602 ; CHECK: add 603 ; CHECK: blr 604 605 ; CHECK-LE: vaddudm 2, 2, 3 606 ; CHECK-LE: blr 607 } 608 609 define <2 x i64> @test27(<2 x i64> %a, <2 x i64> %b) { 610 %v = and <2 x i64> %a, %b 611 ret <2 x i64> %v 612 613 ; CHECK-LABEL: @test27 614 ; CHECK: xxland 34, 34, 35 615 ; CHECK: blr 616 617 ; CHECK-LE-LABEL: @test27 618 ; CHECK-LE: xxland 34, 34, 35 619 ; CHECK-LE: blr 620 } 621 622 define <2 x double> @test28(<2 x double>* %a) { 623 %v = load <2 x double>, <2 x double>* %a, align 16 624 ret <2 x double> %v 625 626 ; CHECK-LABEL: @test28 627 ; CHECK: lxvd2x 34, 0, 3 628 ; CHECK: blr 629 630 ; CHECK-LE-LABEL: @test28 631 ; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 632 ; CHECK-LE: xxswapd 34, [[V1]] 633 ; CHECK-LE: blr 634 } 635 636 define void @test29(<2 x double>* %a, <2 x double> %b) { 637 store <2 x double> %b, <2 x double>* %a, align 16 638 ret void 639 640 ; CHECK-LABEL: @test29 641 ; CHECK: stxvd2x 34, 0, 3 642 ; CHECK: blr 643 644 ; CHECK-LE-LABEL: @test29 645 ; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 646 ; CHECK-LE: stxvd2x [[V1]], 0, 3 647 ; CHECK-LE: blr 648 } 649 650 define <2 x double> @test28u(<2 x double>* %a) { 651 %v = load <2 x double>, <2 x double>* %a, align 8 652 ret <2 x double> %v 653 654 ; CHECK-LABEL: @test28u 655 ; CHECK: lxvd2x 34, 0, 3 656 ; CHECK: blr 657 658 ; CHECK-LE-LABEL: @test28u 659 ; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 660 ; CHECK-LE: xxswapd 34, [[V1]] 661 ; CHECK-LE: blr 662 } 663 664 define void @test29u(<2 x double>* %a, <2 x double> %b) { 665 store <2 x double> %b, <2 x double>* %a, align 8 666 ret void 667 668 ; CHECK-LABEL: @test29u 669 ; CHECK: stxvd2x 34, 0, 3 670 ; CHECK: blr 671 672 ; CHECK-LE-LABEL: @test29u 673 ; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 674 ; CHECK-LE: stxvd2x [[V1]], 0, 3 675 ; CHECK-LE: blr 676 } 677 678 define <2 x i64> @test30(<2 x i64>* %a) { 679 %v = load <2 x i64>, <2 x i64>* %a, align 16 680 ret <2 x i64> %v 681 682 ; CHECK-REG-LABEL: @test30 683 ; CHECK-REG: lxvd2x 34, 0, 3 684 ; CHECK-REG: blr 685 686 ; CHECK-FISL-LABEL: @test30 687 ; CHECK-FISL: lxvd2x 0, 0, 3 688 ; CHECK-FISL: xxlor 34, 0, 0 689 ; CHECK-FISL: vor 3, 2, 2 690 ; CHECK-FISL: vor 2, 3, 3 691 ; CHECK-FISL: blr 692 693 ; CHECK-LE-LABEL: @test30 694 ; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 695 ; CHECK-LE: xxswapd 34, [[V1]] 696 ; CHECK-LE: blr 697 } 698 699 define void @test31(<2 x i64>* %a, <2 x i64> %b) { 700 store <2 x i64> %b, <2 x i64>* %a, align 16 701 ret void 702 703 ; CHECK-LABEL: @test31 704 ; CHECK: stxvd2x 34, 0, 3 705 ; CHECK: blr 706 707 ; CHECK-LE-LABEL: @test31 708 ; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 709 ; CHECK-LE: stxvd2x [[V1]], 0, 3 710 ; CHECK-LE: blr 711 } 712 713 define <4 x float> @test32(<4 x float>* %a) { 714 %v = load <4 x float>, <4 x float>* %a, align 16 715 ret <4 x float> %v 716 717 ; CHECK-REG-LABEL: @test32 718 ; CHECK-REG: lxvw4x 34, 0, 3 719 ; CHECK-REG: blr 720 721 ; CHECK-FISL-LABEL: @test32 722 ; CHECK-FISL: lxvw4x 0, 0, 3 723 ; CHECK-FISL: xxlor 34, 0, 0 724 ; CHECK-FISL: blr 725 726 ; CHECK-LE-LABEL: @test32 727 ; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 728 ; CHECK-LE: xxswapd 34, [[V1]] 729 ; CHECK-LE: blr 730 } 731 732 define void @test33(<4 x float>* %a, <4 x float> %b) { 733 store <4 x float> %b, <4 x float>* %a, align 16 734 ret void 735 736 ; CHECK-REG-LABEL: @test33 737 ; CHECK-REG: stxvw4x 34, 0, 3 738 ; CHECK-REG: blr 739 740 ; CHECK-FISL-LABEL: @test33 741 ; CHECK-FISL: vor 3, 2, 2 742 ; CHECK-FISL: stxvw4x 35, 0, 3 743 ; CHECK-FISL: blr 744 745 ; CHECK-LE-LABEL: @test33 746 ; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 747 ; CHECK-LE: stxvd2x [[V1]], 0, 3 748 ; CHECK-LE: blr 749 } 750 751 define <4 x float> @test32u(<4 x float>* %a) { 752 %v = load <4 x float>, <4 x float>* %a, align 8 753 ret <4 x float> %v 754 755 ; CHECK-LABEL: @test32u 756 ; CHECK-DAG: lvsl 757 ; CHECK-DAG: lvx 758 ; CHECK-DAG: lvx 759 ; CHECK: vperm 2, 760 ; CHECK: blr 761 762 ; CHECK-LE-LABEL: @test32u 763 ; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 764 ; CHECK-LE: xxswapd 34, [[V1]] 765 ; CHECK-LE: blr 766 } 767 768 define void @test33u(<4 x float>* %a, <4 x float> %b) { 769 store <4 x float> %b, <4 x float>* %a, align 8 770 ret void 771 772 ; CHECK-REG-LABEL: @test33u 773 ; CHECK-REG: stxvw4x 34, 0, 3 774 ; CHECK-REG: blr 775 776 ; CHECK-FISL-LABEL: @test33u 777 ; CHECK-FISL: vor 3, 2, 2 778 ; CHECK-FISL: stxvw4x 35, 0, 3 779 ; CHECK-FISL: blr 780 781 ; CHECK-LE-LABEL: @test33u 782 ; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 783 ; CHECK-LE: stxvd2x [[V1]], 0, 3 784 ; CHECK-LE: blr 785 } 786 787 define <4 x i32> @test34(<4 x i32>* %a) { 788 %v = load <4 x i32>, <4 x i32>* %a, align 16 789 ret <4 x i32> %v 790 791 ; CHECK-REG-LABEL: @test34 792 ; CHECK-REG: lxvw4x 34, 0, 3 793 ; CHECK-REG: blr 794 795 ; CHECK-FISL-LABEL: @test34 796 ; CHECK-FISL: lxvw4x 0, 0, 3 797 ; CHECK-FISL: xxlor 34, 0, 0 798 ; CHECK-FISL: blr 799 800 ; CHECK-LE-LABEL: @test34 801 ; CHECK-LE: lxvd2x [[V1:[0-9]+]], 0, 3 802 ; CHECK-LE: xxswapd 34, [[V1]] 803 ; CHECK-LE: blr 804 } 805 806 define void @test35(<4 x i32>* %a, <4 x i32> %b) { 807 store <4 x i32> %b, <4 x i32>* %a, align 16 808 ret void 809 810 ; CHECK-REG-LABEL: @test35 811 ; CHECK-REG: stxvw4x 34, 0, 3 812 ; CHECK-REG: blr 813 814 ; CHECK-FISL-LABEL: @test35 815 ; CHECK-FISL: vor 3, 2, 2 816 ; CHECK-FISL: stxvw4x 35, 0, 3 817 ; CHECK-FISL: blr 818 819 ; CHECK-LE-LABEL: @test35 820 ; CHECK-LE: xxswapd [[V1:[0-9]+]], 34 821 ; CHECK-LE: stxvd2x [[V1]], 0, 3 822 ; CHECK-LE: blr 823 } 824 825 define <2 x double> @test40(<2 x i64> %a) { 826 %v = uitofp <2 x i64> %a to <2 x double> 827 ret <2 x double> %v 828 829 ; CHECK-LABEL: @test40 830 ; CHECK: xvcvuxddp 34, 34 831 ; CHECK: blr 832 833 ; CHECK-LE-LABEL: @test40 834 ; CHECK-LE: xvcvuxddp 34, 34 835 ; CHECK-LE: blr 836 } 837 838 define <2 x double> @test41(<2 x i64> %a) { 839 %v = sitofp <2 x i64> %a to <2 x double> 840 ret <2 x double> %v 841 842 ; CHECK-LABEL: @test41 843 ; CHECK: xvcvsxddp 34, 34 844 ; CHECK: blr 845 846 ; CHECK-LE-LABEL: @test41 847 ; CHECK-LE: xvcvsxddp 34, 34 848 ; CHECK-LE: blr 849 } 850 851 define <2 x i64> @test42(<2 x double> %a) { 852 %v = fptoui <2 x double> %a to <2 x i64> 853 ret <2 x i64> %v 854 855 ; CHECK-LABEL: @test42 856 ; CHECK: xvcvdpuxds 34, 34 857 ; CHECK: blr 858 859 ; CHECK-LE-LABEL: @test42 860 ; CHECK-LE: xvcvdpuxds 34, 34 861 ; CHECK-LE: blr 862 } 863 864 define <2 x i64> @test43(<2 x double> %a) { 865 %v = fptosi <2 x double> %a to <2 x i64> 866 ret <2 x i64> %v 867 868 ; CHECK-LABEL: @test43 869 ; CHECK: xvcvdpsxds 34, 34 870 ; CHECK: blr 871 872 ; CHECK-LE-LABEL: @test43 873 ; CHECK-LE: xvcvdpsxds 34, 34 874 ; CHECK-LE: blr 875 } 876 877 define <2 x float> @test44(<2 x i64> %a) { 878 %v = uitofp <2 x i64> %a to <2 x float> 879 ret <2 x float> %v 880 881 ; CHECK-LABEL: @test44 882 ; FIXME: The code quality here looks pretty bad. 883 ; CHECK: blr 884 } 885 886 define <2 x float> @test45(<2 x i64> %a) { 887 %v = sitofp <2 x i64> %a to <2 x float> 888 ret <2 x float> %v 889 890 ; CHECK-LABEL: @test45 891 ; FIXME: The code quality here looks pretty bad. 892 ; CHECK: blr 893 } 894 895 define <2 x i64> @test46(<2 x float> %a) { 896 %v = fptoui <2 x float> %a to <2 x i64> 897 ret <2 x i64> %v 898 899 ; CHECK-LABEL: @test46 900 ; FIXME: The code quality here looks pretty bad. 901 ; CHECK: blr 902 } 903 904 define <2 x i64> @test47(<2 x float> %a) { 905 %v = fptosi <2 x float> %a to <2 x i64> 906 ret <2 x i64> %v 907 908 ; CHECK-LABEL: @test47 909 ; FIXME: The code quality here looks pretty bad. 910 ; CHECK: blr 911 } 912 913 define <2 x double> @test50(double* %a) { 914 %v = load double, double* %a, align 8 915 %w = insertelement <2 x double> undef, double %v, i32 0 916 %x = insertelement <2 x double> %w, double %v, i32 1 917 ret <2 x double> %x 918 919 ; CHECK-LABEL: @test50 920 ; CHECK: lxvdsx 34, 0, 3 921 ; CHECK: blr 922 923 ; CHECK-LE-LABEL: @test50 924 ; CHECK-LE: lxvdsx 34, 0, 3 925 ; CHECK-LE: blr 926 } 927 928 define <2 x double> @test51(<2 x double> %a, <2 x double> %b) { 929 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 0> 930 ret <2 x double> %v 931 932 ; CHECK-LABEL: @test51 933 ; CHECK: xxspltd 34, 34, 0 934 ; CHECK: blr 935 936 ; CHECK-LE-LABEL: @test51 937 ; CHECK-LE: xxspltd 34, 34, 1 938 ; CHECK-LE: blr 939 } 940 941 define <2 x double> @test52(<2 x double> %a, <2 x double> %b) { 942 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2> 943 ret <2 x double> %v 944 945 ; CHECK-LABEL: @test52 946 ; CHECK: xxmrghd 34, 34, 35 947 ; CHECK: blr 948 949 ; CHECK-LE-LABEL: @test52 950 ; CHECK-LE: xxmrgld 34, 35, 34 951 ; CHECK-LE: blr 952 } 953 954 define <2 x double> @test53(<2 x double> %a, <2 x double> %b) { 955 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 2, i32 0> 956 ret <2 x double> %v 957 958 ; CHECK-LABEL: @test53 959 ; CHECK: xxmrghd 34, 35, 34 960 ; CHECK: blr 961 962 ; CHECK-LE-LABEL: @test53 963 ; CHECK-LE: xxmrgld 34, 34, 35 964 ; CHECK-LE: blr 965 } 966 967 define <2 x double> @test54(<2 x double> %a, <2 x double> %b) { 968 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2> 969 ret <2 x double> %v 970 971 ; CHECK-LABEL: @test54 972 ; CHECK: xxpermdi 34, 34, 35, 2 973 ; CHECK: blr 974 975 ; CHECK-LE-LABEL: @test54 976 ; CHECK-LE: xxpermdi 34, 35, 34, 2 977 ; CHECK-LE: blr 978 } 979 980 define <2 x double> @test55(<2 x double> %a, <2 x double> %b) { 981 %v = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3> 982 ret <2 x double> %v 983 984 ; CHECK-LABEL: @test55 985 ; CHECK: xxmrgld 34, 34, 35 986 ; CHECK: blr 987 988 ; CHECK-LE-LABEL: @test55 989 ; CHECK-LE: xxmrghd 34, 35, 34 990 ; CHECK-LE: blr 991 } 992 993 define <2 x i64> @test56(<2 x i64> %a, <2 x i64> %b) { 994 %v = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3> 995 ret <2 x i64> %v 996 997 ; CHECK-LABEL: @test56 998 ; CHECK: xxmrgld 34, 34, 35 999 ; CHECK: blr 1000 1001 ; CHECK-LE-LABEL: @test56 1002 ; CHECK-LE: xxmrghd 34, 35, 34 1003 ; CHECK-LE: blr 1004 } 1005 1006 define <2 x i64> @test60(<2 x i64> %a, <2 x i64> %b) { 1007 %v = shl <2 x i64> %a, %b 1008 ret <2 x i64> %v 1009 1010 ; CHECK-LABEL: @test60 1011 ; This should scalarize, and the current code quality is not good. 1012 ; CHECK: stxvd2x 1013 ; CHECK: stxvd2x 1014 ; CHECK: sld 1015 ; CHECK: sld 1016 ; CHECK: lxvd2x 1017 ; CHECK: blr 1018 } 1019 1020 define <2 x i64> @test61(<2 x i64> %a, <2 x i64> %b) { 1021 %v = lshr <2 x i64> %a, %b 1022 ret <2 x i64> %v 1023 1024 ; CHECK-LABEL: @test61 1025 ; This should scalarize, and the current code quality is not good. 1026 ; CHECK: stxvd2x 1027 ; CHECK: stxvd2x 1028 ; CHECK: srd 1029 ; CHECK: srd 1030 ; CHECK: lxvd2x 1031 ; CHECK: blr 1032 } 1033 1034 define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) { 1035 %v = ashr <2 x i64> %a, %b 1036 ret <2 x i64> %v 1037 1038 ; CHECK-LABEL: @test62 1039 ; This should scalarize, and the current code quality is not good. 1040 ; CHECK: stxvd2x 1041 ; CHECK: stxvd2x 1042 ; CHECK: srad 1043 ; CHECK: srad 1044 ; CHECK: lxvd2x 1045 ; CHECK: blr 1046 } 1047 1048 define double @test63(<2 x double> %a) { 1049 %v = extractelement <2 x double> %a, i32 0 1050 ret double %v 1051 1052 ; CHECK-REG-LABEL: @test63 1053 ; CHECK-REG: xxlor 1, 34, 34 1054 ; CHECK-REG: blr 1055 1056 ; CHECK-FISL-LABEL: @test63 1057 ; CHECK-FISL: xxlor 0, 34, 34 1058 ; CHECK-FISL: fmr 1, 0 1059 ; CHECK-FISL: blr 1060 1061 ; CHECK-LE-LABEL: @test63 1062 ; CHECK-LE: xxswapd 1, 34 1063 ; CHECK-LE: blr 1064 } 1065 1066 define double @test64(<2 x double> %a) { 1067 %v = extractelement <2 x double> %a, i32 1 1068 ret double %v 1069 1070 ; CHECK-REG-LABEL: @test64 1071 ; CHECK-REG: xxswapd 1, 34 1072 ; CHECK-REG: blr 1073 1074 ; CHECK-FISL-LABEL: @test64 1075 ; CHECK-FISL: xxswapd 34, 34 1076 ; CHECK-FISL: xxlor 0, 34, 34 1077 ; CHECK-FISL: fmr 1, 0 1078 ; CHECK-FISL: blr 1079 1080 ; CHECK-LE-LABEL: @test64 1081 ; CHECK-LE: xxlor 1, 34, 34 1082 } 1083 1084 define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) { 1085 %w = icmp eq <2 x i64> %a, %b 1086 ret <2 x i1> %w 1087 1088 ; CHECK-REG-LABEL: @test65 1089 ; CHECK-REG: vcmpequw 2, 2, 3 1090 ; CHECK-REG: blr 1091 1092 ; CHECK-FISL-LABEL: @test65 1093 ; CHECK-FISL: vor 4, 3, 3 1094 ; CHECK-FISL: vor 5, 2, 2 1095 ; CHECK-FISL: vcmpequw 4, 5, 4 1096 ; CHECK-FISL: vor 2, 4, 4 1097 ; CHECK-FISL: blr 1098 1099 ; CHECK-LE-LABEL: @test65 1100 ; CHECK-LE: vcmpequd 2, 2, 3 1101 ; CHECK-LE: blr 1102 } 1103 1104 define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) { 1105 %w = icmp ne <2 x i64> %a, %b 1106 ret <2 x i1> %w 1107 1108 ; CHECK-REG-LABEL: @test66 1109 ; CHECK-REG: vcmpequw {{[0-9]+}}, 2, 3 1110 ; CHECK-REG: xxlnor 34, {{[0-9]+}}, {{[0-9]+}} 1111 ; CHECK-REG: blr 1112 1113 ; CHECK-FISL-LABEL: @test66 1114 ; CHECK-FISL: vcmpequw {{[0-9]+}}, 5, 4 1115 ; CHECK-FISL: xxlnor 34, {{[0-9]+}}, {{[0-9]+}} 1116 ; CHECK-FISL: blr 1117 1118 ; CHECK-LE-LABEL: @test66 1119 ; CHECK-LE: vcmpequd {{[0-9]+}}, 2, 3 1120 ; CHECK-LE: xxlnor 34, {{[0-9]+}}, {{[0-9]+}} 1121 ; CHECK-LE: blr 1122 } 1123 1124 define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) { 1125 %w = icmp ult <2 x i64> %a, %b 1126 ret <2 x i1> %w 1127 1128 ; CHECK-LABEL: @test67 1129 ; This should scalarize, and the current code quality is not good. 1130 ; CHECK: stxvd2x 1131 ; CHECK: stxvd2x 1132 ; CHECK: cmpld 1133 ; CHECK: cmpld 1134 ; CHECK: lxvd2x 1135 ; CHECK: blr 1136 1137 ; CHECK-LE-LABEL: @test67 1138 ; CHECK-LE: vcmpgtud 2, 3, 2 1139 ; CHECK-LE: blr 1140 } 1141 1142 define <2 x double> @test68(<2 x i32> %a) { 1143 %w = sitofp <2 x i32> %a to <2 x double> 1144 ret <2 x double> %w 1145 1146 ; CHECK-LABEL: @test68 1147 ; CHECK: xxsldwi [[V1:[0-9]+]], 34, 34, 1 1148 ; CHECK: xvcvsxwdp 34, [[V1]] 1149 ; CHECK: blr 1150 1151 ; CHECK-LE-LABEL: @test68 1152 ; CHECK-LE: xxsldwi [[V1:[0-9]+]], 34, 34, 1 1153 ; CHECK-LE: xvcvsxwdp 34, [[V1]] 1154 ; CHECK-LE: blr 1155 } 1156 1157 define <2 x double> @test69(<2 x i16> %a) { 1158 %w = sitofp <2 x i16> %a to <2 x double> 1159 ret <2 x double> %w 1160 1161 ; CHECK-LABEL: @test69 1162 ; CHECK: vspltisw [[V1:[0-9]+]], 8 1163 ; CHECK: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]] 1164 ; CHECK: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]] 1165 ; CHECK: vsraw {{[0-9]+}}, [[V3]], [[V2]] 1166 ; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1 1167 ; CHECK: xvcvsxwdp 34, [[V4]] 1168 ; CHECK: blr 1169 1170 ; CHECK-LE-LABEL: @test69 1171 ; CHECK-LE: vspltisw [[V1:[0-9]+]], 8 1172 ; CHECK-LE: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]] 1173 ; CHECK-LE: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]] 1174 ; CHECK-LE: vsraw {{[0-9]+}}, [[V3]], [[V2]] 1175 ; CHECK-LE: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1 1176 ; CHECK-LE: xvcvsxwdp 34, [[V4]] 1177 ; CHECK-LE: blr 1178 } 1179 1180 define <2 x double> @test70(<2 x i8> %a) { 1181 %w = sitofp <2 x i8> %a to <2 x double> 1182 ret <2 x double> %w 1183 1184 ; CHECK-LABEL: @test70 1185 ; CHECK: vspltisw [[V1:[0-9]+]], 12 1186 ; CHECK: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]] 1187 ; CHECK: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]] 1188 ; CHECK: vsraw {{[0-9]+}}, [[V3]], [[V2]] 1189 ; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1 1190 ; CHECK: xvcvsxwdp 34, [[V4]] 1191 ; CHECK: blr 1192 1193 ; CHECK-LE-LABEL: @test70 1194 ; CHECK-LE: vspltisw [[V1:[0-9]+]], 12 1195 ; CHECK-LE: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]] 1196 ; CHECK-LE: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]] 1197 ; CHECK-LE: vsraw {{[0-9]+}}, [[V3]], [[V2]] 1198 ; CHECK-LE: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1 1199 ; CHECK-LE: xvcvsxwdp 34, [[V4]] 1200 ; CHECK-LE: blr 1201 } 1202 1203 define <2 x i32> @test80(i32 %v) { 1204 %b1 = insertelement <2 x i32> undef, i32 %v, i32 0 1205 %b2 = shufflevector <2 x i32> %b1, <2 x i32> undef, <2 x i32> zeroinitializer 1206 %i = add <2 x i32> %b2, <i32 2, i32 3> 1207 ret <2 x i32> %i 1208 1209 ; CHECK-REG-LABEL: @test80 1210 ; CHECK-REG-DAG: addi [[R1:[0-9]+]], 3, 3 1211 ; CHECK-REG-DAG: addi [[R2:[0-9]+]], 1, -16 1212 ; CHECK-REG-DAG: addi [[R3:[0-9]+]], 3, 2 1213 ; CHECK-REG: std [[R1]], -8(1) 1214 ; CHECK-REG: std [[R3]], -16(1) 1215 ; CHECK-REG: lxvd2x 34, 0, [[R2]] 1216 ; CHECK-REG-NOT: stxvd2x 1217 ; CHECK-REG: blr 1218 1219 ; CHECK-FISL-LABEL: @test80 1220 ; CHECK-FISL-DAG: addi [[R1:[0-9]+]], 3, 3 1221 ; CHECK-FISL-DAG: addi [[R2:[0-9]+]], 1, -16 1222 ; CHECK-FISL-DAG: addi [[R3:[0-9]+]], 3, 2 1223 ; CHECK-FISL-DAG: std [[R1]], -8(1) 1224 ; CHECK-FISL-DAG: std [[R3]], -16(1) 1225 ; CHECK-FISL-DAG: lxvd2x 0, 0, [[R2]] 1226 ; CHECK-FISL: blr 1227 1228 ; CHECK-LE-LABEL: @test80 1229 ; CHECK-LE-DAG: mtvsrd [[R1:[0-9]+]], 3 1230 ; CHECK-LE-DAG: addi [[R2:[0-9]+]], {{[0-9]+}}, .LCPI 1231 ; CHECK-LE-DAG: lxvd2x [[V2:[0-9]+]], 0, [[R2]] 1232 ; CHECK-LE-DAG: xxspltd 34, [[R1]] 1233 ; CHECK-LE-DAG: xxswapd 35, [[V2]] 1234 ; CHECK-LE: vaddudm 2, 2, 3 1235 ; CHECK-LE: blr 1236 } 1237 1238 define <2 x double> @test81(<4 x float> %b) { 1239 %w = bitcast <4 x float> %b to <2 x double> 1240 ret <2 x double> %w 1241 1242 ; CHECK-LABEL: @test81 1243 ; CHECK: blr 1244 1245 ; CHECK-LE-LABEL: @test81 1246 ; CHECK-LE: blr 1247 } 1248 1249 define double @test82(double %a, double %b, double %c, double %d) { 1250 entry: 1251 %m = fcmp oeq double %c, %d 1252 %v = select i1 %m, double %a, double %b 1253 ret double %v 1254 1255 ; CHECK-REG-LABEL: @test82 1256 ; CHECK-REG: xscmpudp [[REG:[0-9]+]], 3, 4 1257 ; CHECK-REG: beqlr [[REG]] 1258 1259 ; CHECK-FISL-LABEL: @test82 1260 ; CHECK-FISL: xscmpudp [[REG:[0-9]+]], 3, 4 1261 ; CHECK-FISL: beq [[REG]], {{.*}} 1262 1263 ; CHECK-LE-LABEL: @test82 1264 ; CHECK-LE: xscmpudp [[REG:[0-9]+]], 3, 4 1265 ; CHECK-LE: beqlr [[REG]] 1266 } 1267
