1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx --show-mc-encoding | FileCheck %s 2 3 ; CHECK-LABEL: sitof32 4 ; CHECK: vcvtdq2ps %zmm 5 ; CHECK: ret 6 define <16 x float> @sitof32(<16 x i32> %a) nounwind { 7 %b = sitofp <16 x i32> %a to <16 x float> 8 ret <16 x float> %b 9 } 10 11 ; CHECK-LABEL: sltof864 12 ; CHECK: vcvtqq2pd 13 define <8 x double> @sltof864(<8 x i64> %a) { 14 %b = sitofp <8 x i64> %a to <8 x double> 15 ret <8 x double> %b 16 } 17 18 ; CHECK-LABEL: sltof464 19 ; CHECK: vcvtqq2pd 20 define <4 x double> @sltof464(<4 x i64> %a) { 21 %b = sitofp <4 x i64> %a to <4 x double> 22 ret <4 x double> %b 23 } 24 25 ; CHECK-LABEL: sltof2f32 26 ; CHECK: vcvtqq2ps 27 define <2 x float> @sltof2f32(<2 x i64> %a) { 28 %b = sitofp <2 x i64> %a to <2 x float> 29 ret <2 x float>%b 30 } 31 32 ; CHECK-LABEL: sltof4f32_mem 33 ; CHECK: vcvtqq2psy (%rdi) 34 define <4 x float> @sltof4f32_mem(<4 x i64>* %a) { 35 %a1 = load <4 x i64>, <4 x i64>* %a, align 8 36 %b = sitofp <4 x i64> %a1 to <4 x float> 37 ret <4 x float>%b 38 } 39 40 ; CHECK-LABEL: f64tosl 41 ; CHECK: vcvttpd2qq 42 define <4 x i64> @f64tosl(<4 x double> %a) { 43 %b = fptosi <4 x double> %a to <4 x i64> 44 ret <4 x i64> %b 45 } 46 47 ; CHECK-LABEL: f32tosl 48 ; CHECK: vcvttps2qq 49 define <4 x i64> @f32tosl(<4 x float> %a) { 50 %b = fptosi <4 x float> %a to <4 x i64> 51 ret <4 x i64> %b 52 } 53 54 ; CHECK-LABEL: sltof432 55 ; CHECK: vcvtqq2ps 56 define <4 x float> @sltof432(<4 x i64> %a) { 57 %b = sitofp <4 x i64> %a to <4 x float> 58 ret <4 x float> %b 59 } 60 61 ; CHECK-LABEL: ultof432 62 ; CHECK: vcvtuqq2ps 63 define <4 x float> @ultof432(<4 x i64> %a) { 64 %b = uitofp <4 x i64> %a to <4 x float> 65 ret <4 x float> %b 66 } 67 68 ; CHECK-LABEL: ultof64 69 ; CHECK: vcvtuqq2pd 70 define <8 x double> @ultof64(<8 x i64> %a) { 71 %b = uitofp <8 x i64> %a to <8 x double> 72 ret <8 x double> %b 73 } 74 75 ; CHECK-LABEL: fptosi00 76 ; CHECK: vcvttps2dq %zmm 77 ; CHECK: ret 78 define <16 x i32> @fptosi00(<16 x float> %a) nounwind { 79 %b = fptosi <16 x float> %a to <16 x i32> 80 ret <16 x i32> %b 81 } 82 83 ; CHECK-LABEL: fptoui00 84 ; CHECK: vcvttps2udq 85 ; CHECK: ret 86 define <16 x i32> @fptoui00(<16 x float> %a) nounwind { 87 %b = fptoui <16 x float> %a to <16 x i32> 88 ret <16 x i32> %b 89 } 90 91 ; CHECK-LABEL: fptoui_256 92 ; CHECK: vcvttps2udq 93 ; CHECK: ret 94 define <8 x i32> @fptoui_256(<8 x float> %a) nounwind { 95 %b = fptoui <8 x float> %a to <8 x i32> 96 ret <8 x i32> %b 97 } 98 99 ; CHECK-LABEL: fptoui_128 100 ; CHECK: vcvttps2udq 101 ; CHECK: ret 102 define <4 x i32> @fptoui_128(<4 x float> %a) nounwind { 103 %b = fptoui <4 x float> %a to <4 x i32> 104 ret <4 x i32> %b 105 } 106 107 ; CHECK-LABEL: fptoui01 108 ; CHECK: vcvttpd2udq 109 ; CHECK: ret 110 define <8 x i32> @fptoui01(<8 x double> %a) nounwind { 111 %b = fptoui <8 x double> %a to <8 x i32> 112 ret <8 x i32> %b 113 } 114 115 ; CHECK-LABEL: sitof64 116 ; CHECK: vcvtdq2pd %ymm 117 ; CHECK: ret 118 define <8 x double> @sitof64(<8 x i32> %a) { 119 %b = sitofp <8 x i32> %a to <8 x double> 120 ret <8 x double> %b 121 } 122 123 ; CHECK-LABEL: fptosi01 124 ; CHECK: vcvttpd2dq %zmm 125 ; CHECK: ret 126 define <8 x i32> @fptosi01(<8 x double> %a) { 127 %b = fptosi <8 x double> %a to <8 x i32> 128 ret <8 x i32> %b 129 } 130 131 ; CHECK-LABEL: fptosi03 132 ; CHECK: vcvttpd2dq %ymm 133 ; CHECK: ret 134 define <4 x i32> @fptosi03(<4 x double> %a) { 135 %b = fptosi <4 x double> %a to <4 x i32> 136 ret <4 x i32> %b 137 } 138 139 ; CHECK-LABEL: fptrunc00 140 ; CHECK: vcvtpd2ps %zmm 141 ; CHECK-NEXT: vcvtpd2ps %zmm 142 ; CHECK-NEXT: vinsertf 143 ; CHECK: ret 144 define <16 x float> @fptrunc00(<16 x double> %b) nounwind { 145 %a = fptrunc <16 x double> %b to <16 x float> 146 ret <16 x float> %a 147 } 148 149 ; CHECK-LABEL: fptrunc01 150 ; CHECK: vcvtpd2ps %ymm 151 define <4 x float> @fptrunc01(<4 x double> %b) { 152 %a = fptrunc <4 x double> %b to <4 x float> 153 ret <4 x float> %a 154 } 155 156 ; CHECK-LABEL: fptrunc02 157 ; CHECK: vcvtpd2ps %ymm0, %xmm0 {%k1} {z} 158 define <4 x float> @fptrunc02(<4 x double> %b, <4 x i1> %mask) { 159 %a = fptrunc <4 x double> %b to <4 x float> 160 %c = select <4 x i1>%mask, <4 x float>%a, <4 x float> zeroinitializer 161 ret <4 x float> %c 162 } 163 164 ; CHECK-LABEL: fpext00 165 ; CHECK: vcvtps2pd %ymm0, %zmm0 166 ; CHECK: ret 167 define <8 x double> @fpext00(<8 x float> %b) nounwind { 168 %a = fpext <8 x float> %b to <8 x double> 169 ret <8 x double> %a 170 } 171 172 ; CHECK-LABEL: fpext01 173 ; CHECK: vcvtps2pd %xmm0, %ymm0 {%k1} {z} 174 ; CHECK: ret 175 define <4 x double> @fpext01(<4 x float> %b, <4 x double>%b1, <4 x double>%a1) { 176 %a = fpext <4 x float> %b to <4 x double> 177 %mask = fcmp ogt <4 x double>%a1, %b1 178 %c = select <4 x i1>%mask, <4 x double>%a, <4 x double>zeroinitializer 179 ret <4 x double> %c 180 } 181 182 ; CHECK-LABEL: funcA 183 ; CHECK: vcvtsi2sdq (%rdi){{.*}} encoding: [0x62 184 ; CHECK: ret 185 define double @funcA(i64* nocapture %e) { 186 entry: 187 %tmp1 = load i64, i64* %e, align 8 188 %conv = sitofp i64 %tmp1 to double 189 ret double %conv 190 } 191 192 ; CHECK-LABEL: funcB 193 ; CHECK: vcvtsi2sdl (%{{.*}} encoding: [0x62 194 ; CHECK: ret 195 define double @funcB(i32* %e) { 196 entry: 197 %tmp1 = load i32, i32* %e, align 4 198 %conv = sitofp i32 %tmp1 to double 199 ret double %conv 200 } 201 202 ; CHECK-LABEL: funcC 203 ; CHECK: vcvtsi2ssl (%{{.*}} encoding: [0x62 204 ; CHECK: ret 205 define float @funcC(i32* %e) { 206 entry: 207 %tmp1 = load i32, i32* %e, align 4 208 %conv = sitofp i32 %tmp1 to float 209 ret float %conv 210 } 211 212 ; CHECK-LABEL: i64tof32 213 ; CHECK: vcvtsi2ssq (%{{.*}} encoding: [0x62 214 ; CHECK: ret 215 define float @i64tof32(i64* %e) { 216 entry: 217 %tmp1 = load i64, i64* %e, align 8 218 %conv = sitofp i64 %tmp1 to float 219 ret float %conv 220 } 221 222 ; CHECK-LABEL: fpext 223 ; CHECK: vcvtss2sd {{.*}} encoding: [0x62 224 ; CHECK: ret 225 define void @fpext() { 226 entry: 227 %f = alloca float, align 4 228 %d = alloca double, align 8 229 %tmp = load float, float* %f, align 4 230 %conv = fpext float %tmp to double 231 store double %conv, double* %d, align 8 232 ret void 233 } 234 235 ; CHECK-LABEL: fpround_scalar 236 ; CHECK: vmovsd {{.*}} encoding: [0x62 237 ; CHECK: vcvtsd2ss {{.*}} encoding: [0x62 238 ; CHECK: vmovss {{.*}} encoding: [0x62 239 ; CHECK: ret 240 define void @fpround_scalar() nounwind uwtable { 241 entry: 242 %f = alloca float, align 4 243 %d = alloca double, align 8 244 %tmp = load double, double* %d, align 8 245 %conv = fptrunc double %tmp to float 246 store float %conv, float* %f, align 4 247 ret void 248 } 249 250 ; CHECK-LABEL: long_to_double 251 ; CHECK: vmovq {{.*}} encoding: [0x62 252 ; CHECK: ret 253 define double @long_to_double(i64 %x) { 254 %res = bitcast i64 %x to double 255 ret double %res 256 } 257 258 ; CHECK-LABEL: double_to_long 259 ; CHECK: vmovq {{.*}} encoding: [0x62 260 ; CHECK: ret 261 define i64 @double_to_long(double %x) { 262 %res = bitcast double %x to i64 263 ret i64 %res 264 } 265 266 ; CHECK-LABEL: int_to_float 267 ; CHECK: vmovd {{.*}} encoding: [0x62 268 ; CHECK: ret 269 define float @int_to_float(i32 %x) { 270 %res = bitcast i32 %x to float 271 ret float %res 272 } 273 274 ; CHECK-LABEL: float_to_int 275 ; CHECK: vmovd {{.*}} encoding: [0x62 276 ; CHECK: ret 277 define i32 @float_to_int(float %x) { 278 %res = bitcast float %x to i32 279 ret i32 %res 280 } 281 282 define <16 x double> @uitof64(<16 x i32> %a) nounwind { 283 ; CHECK-LABEL: uitof64: 284 ; CHECK: ## BB#0: 285 ; CHECK-NEXT: vcvtudq2pd %ymm0, %zmm2 286 ; CHECK-NEXT: vextracti32x8 $1, %zmm0, %ymm0 287 ; CHECK-NEXT: vcvtudq2pd %ymm0, %zmm1 288 ; CHECK-NEXT: vmovaps %zmm2, %zmm0 289 ; CHECK-NEXT: retq 290 %b = uitofp <16 x i32> %a to <16 x double> 291 ret <16 x double> %b 292 } 293 294 ; CHECK-LABEL: uitof64_256 295 ; CHECK: vcvtudq2pd 296 ; CHECK: ret 297 define <4 x double> @uitof64_256(<4 x i32> %a) nounwind { 298 %b = uitofp <4 x i32> %a to <4 x double> 299 ret <4 x double> %b 300 } 301 302 ; CHECK-LABEL: uitof32 303 ; CHECK: vcvtudq2ps 304 ; CHECK: ret 305 define <16 x float> @uitof32(<16 x i32> %a) nounwind { 306 %b = uitofp <16 x i32> %a to <16 x float> 307 ret <16 x float> %b 308 } 309 310 ; CHECK-LABEL: uitof32_256 311 ; CHECK: vcvtudq2ps 312 ; CHECK: ret 313 define <8 x float> @uitof32_256(<8 x i32> %a) nounwind { 314 %b = uitofp <8 x i32> %a to <8 x float> 315 ret <8 x float> %b 316 } 317 318 ; CHECK-LABEL: uitof32_128 319 ; CHECK: vcvtudq2ps 320 ; CHECK: ret 321 define <4 x float> @uitof32_128(<4 x i32> %a) nounwind { 322 %b = uitofp <4 x i32> %a to <4 x float> 323 ret <4 x float> %b 324 } 325 326 ; CHECK-LABEL: @fptosi02 327 ; CHECK: vcvttss2si {{.*}} encoding: [0x62 328 ; CHECK: ret 329 define i32 @fptosi02(float %a) nounwind { 330 %b = fptosi float %a to i32 331 ret i32 %b 332 } 333 334 ; CHECK-LABEL: @fptoui02 335 ; CHECK: vcvttss2usi {{.*}} encoding: [0x62 336 ; CHECK: ret 337 define i32 @fptoui02(float %a) nounwind { 338 %b = fptoui float %a to i32 339 ret i32 %b 340 } 341 342 ; CHECK-LABEL: @uitofp02 343 ; CHECK: vcvtusi2ss 344 ; CHECK: ret 345 define float @uitofp02(i32 %a) nounwind { 346 %b = uitofp i32 %a to float 347 ret float %b 348 } 349 350 ; CHECK-LABEL: @uitofp03 351 ; CHECK: vcvtusi2sd 352 ; CHECK: ret 353 define double @uitofp03(i32 %a) nounwind { 354 %b = uitofp i32 %a to double 355 ret double %b 356 } 357 358 ; CHECK-LABEL: @sitofp_16i1_float 359 ; CHECK: vpmovm2d 360 ; CHECK: vcvtdq2ps 361 define <16 x float> @sitofp_16i1_float(<16 x i32> %a) { 362 %mask = icmp slt <16 x i32> %a, zeroinitializer 363 %1 = sitofp <16 x i1> %mask to <16 x float> 364 ret <16 x float> %1 365 } 366 367 ; CHECK-LABEL: @sitofp_16i8_float 368 ; CHECK: vpmovsxbd 369 ; CHECK: vcvtdq2ps 370 define <16 x float> @sitofp_16i8_float(<16 x i8> %a) { 371 %1 = sitofp <16 x i8> %a to <16 x float> 372 ret <16 x float> %1 373 } 374 375 ; CHECK-LABEL: @sitofp_16i16_float 376 ; CHECK: vpmovsxwd 377 ; CHECK: vcvtdq2ps 378 define <16 x float> @sitofp_16i16_float(<16 x i16> %a) { 379 %1 = sitofp <16 x i16> %a to <16 x float> 380 ret <16 x float> %1 381 } 382 383 ; CHECK-LABEL: @sitofp_8i16_double 384 ; CHECK: vpmovsxwd 385 ; CHECK: vcvtdq2pd 386 define <8 x double> @sitofp_8i16_double(<8 x i16> %a) { 387 %1 = sitofp <8 x i16> %a to <8 x double> 388 ret <8 x double> %1 389 } 390 391 ; CHECK-LABEL: sitofp_8i8_double 392 ; CHECK: vpmovzxwd 393 ; CHECK: vpslld 394 ; CHECK: vpsrad 395 ; CHECK: vcvtdq2pd 396 define <8 x double> @sitofp_8i8_double(<8 x i8> %a) { 397 %1 = sitofp <8 x i8> %a to <8 x double> 398 ret <8 x double> %1 399 } 400 401 402 ; CHECK-LABEL: @sitofp_8i1_double 403 ; CHECK: vpmovm2d 404 ; CHECK: vcvtdq2pd 405 define <8 x double> @sitofp_8i1_double(<8 x double> %a) { 406 %cmpres = fcmp ogt <8 x double> %a, zeroinitializer 407 %1 = sitofp <8 x i1> %cmpres to <8 x double> 408 ret <8 x double> %1 409 } 410 411 ; CHECK-LABEL: @uitofp_16i8 412 ; CHECK: vpmovzxbd 413 ; CHECK: vcvtudq2ps 414 define <16 x float> @uitofp_16i8(<16 x i8>%a) { 415 %b = uitofp <16 x i8> %a to <16 x float> 416 ret <16 x float>%b 417 } 418 419 ; CHECK-LABEL: @uitofp_16i16 420 ; CHECK: vpmovzxwd 421 ; CHECK: vcvtudq2ps 422 define <16 x float> @uitofp_16i16(<16 x i16>%a) { 423 %b = uitofp <16 x i16> %a to <16 x float> 424 ret <16 x float>%b 425 } 426 427
