1 ; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mcpu=penryn -mattr=sse4.1 | FileCheck %s --check-prefix=X32 2 ; RUN: llc < %s -mtriple=x86_64-linux -mcpu=penryn -mattr=sse4.1 | FileCheck %s --check-prefix=X64 3 ; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=penryn -mattr=sse4.1 | FileCheck %s --check-prefix=X64 4 5 define i32 @test1() nounwind readonly { 6 ; X32-LABEL: test1: 7 ; X32: # BB#0: # %entry 8 ; X32-NEXT: movl %gs:196, %eax 9 ; X32-NEXT: movl (%eax), %eax 10 ; X32-NEXT: retl 11 ; 12 ; X64-LABEL: test1: 13 ; X64: # BB#0: # %entry 14 ; X64-NEXT: movq %gs:320, %rax 15 ; X64-NEXT: movl (%rax), %eax 16 ; X64-NEXT: retq 17 entry: 18 %tmp = load i32*, i32* addrspace(256)* getelementptr (i32*, i32* addrspace(256)* inttoptr (i32 72 to i32* addrspace(256)*), i32 31) ; <i32*> [#uses=1] 19 %tmp1 = load i32, i32* %tmp ; <i32> [#uses=1] 20 ret i32 %tmp1 21 } 22 23 define i64 @test2(void (i8*)* addrspace(256)* %tmp8) nounwind { 24 ; X32-LABEL: test2: 25 ; X32: # BB#0: # %entry 26 ; X32-NEXT: subl $12, %esp 27 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax 28 ; X32-NEXT: calll *%gs:(%eax) 29 ; X32-NEXT: xorl %eax, %eax 30 ; X32-NEXT: xorl %edx, %edx 31 ; X32-NEXT: addl $12, %esp 32 ; X32-NEXT: retl 33 ; 34 ; X64-LABEL: test2: 35 ; X64: # BB#0: # %entry 36 ; X64-NEXT: {{(subq.*%rsp|pushq)}} 37 ; X64-NEXT: callq *%gs:(%{{(rcx|rdi)}}) 38 ; X64-NEXT: xorl %eax, %eax 39 ; X64-NEXT: {{(addq.*%rsp|popq)}} 40 ; X64-NEXT: retq 41 entry: 42 %tmp9 = load void (i8*)*, void (i8*)* addrspace(256)* %tmp8, align 8 43 tail call void %tmp9(i8* undef) nounwind optsize 44 ret i64 0 45 } 46 47 define <2 x i64> @pmovsxwd_1(i64 addrspace(256)* %p) nounwind readonly { 48 ; X32-LABEL: pmovsxwd_1: 49 ; X32: # BB#0: # %entry 50 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax 51 ; X32-NEXT: pmovsxwd %gs:(%eax), %xmm0 52 ; X32-NEXT: retl 53 ; 54 ; X64-LABEL: pmovsxwd_1: 55 ; X64: # BB#0: # %entry 56 ; X64-NEXT: pmovsxwd %gs:(%{{(rcx|rdi)}}), %xmm0 57 ; X64-NEXT: retq 58 entry: 59 %0 = load i64, i64 addrspace(256)* %p 60 %tmp2 = insertelement <2 x i64> zeroinitializer, i64 %0, i32 0 61 %1 = bitcast <2 x i64> %tmp2 to <8 x i16> 62 %2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone 63 %3 = bitcast <4 x i32> %2 to <2 x i64> 64 ret <2 x i64> %3 65 } 66 67 ; The two loads here both look identical to selection DAG, except for their 68 ; address spaces. Make sure they aren't CSE'd. 69 define i32 @test_no_cse() nounwind readonly { 70 ; X32-LABEL: test_no_cse: 71 ; X32: # BB#0: # %entry 72 ; X32-NEXT: movl %gs:196, %eax 73 ; X32-NEXT: movl (%eax), %eax 74 ; X32-NEXT: movl %fs:196, %ecx 75 ; X32-NEXT: addl (%ecx), %eax 76 ; X32-NEXT: retl 77 ; 78 ; X64-LABEL: test_no_cse: 79 ; X64: # BB#0: # %entry 80 ; X64-NEXT: movq %gs:320, %rax 81 ; X64-NEXT: movl (%rax), %eax 82 ; X64-NEXT: movq %fs:320, %rcx 83 ; X64-NEXT: addl (%rcx), %eax 84 ; X64-NEXT: retq 85 entry: 86 %tmp = load i32*, i32* addrspace(256)* getelementptr (i32*, i32* addrspace(256)* inttoptr (i32 72 to i32* addrspace(256)*), i32 31) ; <i32*> [#uses=1] 87 %tmp1 = load i32, i32* %tmp ; <i32> [#uses=1] 88 %tmp2 = load i32*, i32* addrspace(257)* getelementptr (i32*, i32* addrspace(257)* inttoptr (i32 72 to i32* addrspace(257)*), i32 31) ; <i32*> [#uses=1] 89 %tmp3 = load i32, i32* %tmp2 ; <i32> [#uses=1] 90 %tmp4 = add i32 %tmp1, %tmp3 91 ret i32 %tmp4 92 } 93 94 declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone 95
