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      1 ; RUN: llc < %s -march=x86-64 -mcpu=penryn -mattr=+avx2 | FileCheck %s
      2 
      3 
      4 define <8 x i16> @sdiv_vec8x16(<8 x i16> %var) {
      5 entry:
      6 ; CHECK: sdiv_vec8x16
      7 ; CHECK: psraw  $15
      8 ; CHECK: vpsrlw  $11
      9 ; CHECK: vpaddw
     10 ; CHECK: vpsraw  $5
     11 ; CHECK: ret
     12   %0 = sdiv <8 x i16> %var, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>
     13   ret <8 x i16> %0
     14 }
     15 
     16 define <8 x i16> @sdiv_vec8x16_minsize(<8 x i16> %var) minsize {
     17 entry:
     18 ; CHECK: sdiv_vec8x16_minsize
     19 ; CHECK: psraw  $15
     20 ; CHECK: vpsrlw  $11
     21 ; CHECK: vpaddw
     22 ; CHECK: vpsraw  $5
     23 ; CHECK: ret
     24   %0 = sdiv <8 x i16> %var, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>
     25   ret <8 x i16> %0
     26 }
     27 
     28 
     29 define <4 x i32> @sdiv_zero(<4 x i32> %var) {
     30 entry:
     31 ; CHECK: sdiv_zero
     32 ; CHECK-NOT: sra
     33 ; CHECK: ret
     34   %0 = sdiv <4 x i32> %var, <i32 0, i32 0, i32 0, i32 0>
     35   ret <4 x i32> %0
     36 }
     37 
     38 define <4 x i32> @sdiv_vec4x32(<4 x i32> %var) {
     39 entry:
     40 ; CHECK: sdiv_vec4x32
     41 ; CHECK: vpsrad $31
     42 ; CHECK: vpsrld $28
     43 ; CHECK: vpaddd
     44 ; CHECK: vpsrad $4
     45 ; CHECK: ret
     46 %0 = sdiv <4 x i32> %var, <i32 16, i32 16, i32 16, i32 16>
     47 ret <4 x i32> %0
     48 }
     49 
     50 define <4 x i32> @sdiv_negative(<4 x i32> %var) {
     51 entry:
     52 ; CHECK: sdiv_negative
     53 ; CHECK: vpsrad $31
     54 ; CHECK: vpsrld $28
     55 ; CHECK: vpaddd
     56 ; CHECK: vpsrad $4
     57 ; CHECK: vpsubd
     58 ; CHECK: ret
     59 %0 = sdiv <4 x i32> %var, <i32 -16, i32 -16, i32 -16, i32 -16>
     60 ret <4 x i32> %0
     61 }
     62 
     63 define <8 x i32> @sdiv8x32(<8 x i32> %var) {
     64 entry:
     65 ; CHECK: sdiv8x32
     66 ; CHECK: vpsrad $31
     67 ; CHECK: vpsrld $26
     68 ; CHECK: vpaddd
     69 ; CHECK: vpsrad $6
     70 ; CHECK: ret
     71 %0 = sdiv <8 x i32> %var, <i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64, i32 64>
     72 ret <8 x i32> %0
     73 }
     74 
     75 define <16 x i16> @sdiv16x16(<16 x i16> %var) {
     76 entry:
     77 ; CHECK: sdiv16x16
     78 ; CHECK: vpsraw  $15
     79 ; CHECK: vpsrlw  $14
     80 ; CHECK: vpaddw
     81 ; CHECK: vpsraw  $2
     82 ; CHECK: ret
     83   %a0 = sdiv <16 x i16> %var, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
     84   ret <16 x i16> %a0
     85 }
     86 
     87 ; CHECK: sdiv_non_splat
     88 ; CHECK: idivl
     89 ; CHECK: ret
     90 define <4 x i32> @sdiv_non_splat(<4 x i32> %x) {
     91   %y = sdiv <4 x i32> %x, <i32 2, i32 0, i32 0, i32 0>
     92   ret <4 x i32> %y
     93 }
     94