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      1 #ifndef __UAPI_RADIO_IRIS_COMMANDS_H
      2 #define __UAPI_RADIO_IRIS_COMMANDS_H
      3 
      4 enum v4l2_cid_private_iris_t {
      5 	V4L2_CID_PRIVATE_IRIS_SRCHMODE = (0x08000000 + 1),
      6 	V4L2_CID_PRIVATE_IRIS_SCANDWELL,
      7 	V4L2_CID_PRIVATE_IRIS_SRCHON,
      8 	V4L2_CID_PRIVATE_IRIS_STATE,
      9 	V4L2_CID_PRIVATE_IRIS_TRANSMIT_MODE,
     10 	V4L2_CID_PRIVATE_IRIS_RDSGROUP_MASK,
     11 	V4L2_CID_PRIVATE_IRIS_REGION,
     12 	V4L2_CID_PRIVATE_IRIS_SIGNAL_TH,
     13 	V4L2_CID_PRIVATE_IRIS_SRCH_PTY,
     14 	V4L2_CID_PRIVATE_IRIS_SRCH_PI,
     15 	V4L2_CID_PRIVATE_IRIS_SRCH_CNT,
     16 	V4L2_CID_PRIVATE_IRIS_EMPHASIS,
     17 	V4L2_CID_PRIVATE_IRIS_RDS_STD,
     18 	V4L2_CID_PRIVATE_IRIS_SPACING,
     19 	V4L2_CID_PRIVATE_IRIS_RDSON,
     20 	V4L2_CID_PRIVATE_IRIS_RDSGROUP_PROC,
     21 	V4L2_CID_PRIVATE_IRIS_LP_MODE,
     22 	V4L2_CID_PRIVATE_IRIS_ANTENNA,
     23 	V4L2_CID_PRIVATE_IRIS_RDSD_BUF,
     24 	V4L2_CID_PRIVATE_IRIS_PSALL,  /*0x8000014*/
     25 
     26 	/*v4l2 Tx controls*/
     27 	V4L2_CID_PRIVATE_IRIS_TX_SETPSREPEATCOUNT,
     28 	V4L2_CID_PRIVATE_IRIS_STOP_RDS_TX_PS_NAME,
     29 	V4L2_CID_PRIVATE_IRIS_STOP_RDS_TX_RT,
     30 	V4L2_CID_PRIVATE_IRIS_IOVERC,
     31 	V4L2_CID_PRIVATE_IRIS_INTDET,
     32 	V4L2_CID_PRIVATE_IRIS_MPX_DCC,
     33 	V4L2_CID_PRIVATE_IRIS_AF_JUMP,
     34 	V4L2_CID_PRIVATE_IRIS_RSSI_DELTA,
     35 	V4L2_CID_PRIVATE_IRIS_HLSI, /*0x800001d*/
     36 
     37 	/*Diagnostic commands*/
     38 	V4L2_CID_PRIVATE_IRIS_SOFT_MUTE,
     39 	V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_ADDR,
     40 	V4L2_CID_PRIVATE_IRIS_RIVA_ACCS_LEN,
     41 	V4L2_CID_PRIVATE_IRIS_RIVA_PEEK,
     42 	V4L2_CID_PRIVATE_IRIS_RIVA_POKE,
     43 	V4L2_CID_PRIVATE_IRIS_SSBI_ACCS_ADDR,
     44 	V4L2_CID_PRIVATE_IRIS_SSBI_PEEK,
     45 	V4L2_CID_PRIVATE_IRIS_SSBI_POKE,
     46 	V4L2_CID_PRIVATE_IRIS_TX_TONE,
     47 	V4L2_CID_PRIVATE_IRIS_RDS_GRP_COUNTERS,
     48 	V4L2_CID_PRIVATE_IRIS_SET_NOTCH_FILTER, /* 0x8000028 */
     49 	V4L2_CID_PRIVATE_IRIS_SET_AUDIO_PATH, /* TAVARUA specific command */
     50 	V4L2_CID_PRIVATE_IRIS_DO_CALIBRATION,
     51 	V4L2_CID_PRIVATE_IRIS_SRCH_ALGORITHM, /* TAVARUA specific command */
     52 	V4L2_CID_PRIVATE_IRIS_GET_SINR,
     53 	V4L2_CID_PRIVATE_INTF_LOW_THRESHOLD,
     54 	V4L2_CID_PRIVATE_INTF_HIGH_THRESHOLD,
     55 	V4L2_CID_PRIVATE_SINR_THRESHOLD,
     56 	V4L2_CID_PRIVATE_SINR_SAMPLES,
     57 	V4L2_CID_PRIVATE_SPUR_FREQ,
     58 	V4L2_CID_PRIVATE_SPUR_FREQ_RMSSI,
     59 	V4L2_CID_PRIVATE_SPUR_SELECTION,
     60 	V4L2_CID_PRIVATE_UPDATE_SPUR_TABLE,
     61 	V4L2_CID_PRIVATE_VALID_CHANNEL,
     62 	V4L2_CID_PRIVATE_AF_RMSSI_TH,
     63 	V4L2_CID_PRIVATE_AF_RMSSI_SAMPLES,
     64 	V4L2_CID_PRIVATE_GOOD_CH_RMSSI_TH,
     65 	V4L2_CID_PRIVATE_SRCHALGOTYPE,
     66 	V4L2_CID_PRIVATE_CF0TH12,
     67 	V4L2_CID_PRIVATE_SINRFIRSTSTAGE,
     68 	V4L2_CID_PRIVATE_RMSSIFIRSTSTAGE,
     69 	V4L2_CID_PRIVATE_RXREPEATCOUNT,
     70 	V4L2_CID_PRIVATE_IRIS_RSSI_TH,
     71 	V4L2_CID_PRIVATE_IRIS_AF_JUMP_RSSI_TH,
     72 	V4L2_CID_PRIVATE_BLEND_SINRHI,
     73 	V4L2_CID_PRIVATE_BLEND_RMSSIHI,
     74 
     75 	/*using private CIDs under userclass*/
     76 	V4L2_CID_PRIVATE_IRIS_READ_DEFAULT = 0x00980928,
     77 	V4L2_CID_PRIVATE_IRIS_WRITE_DEFAULT,
     78 	V4L2_CID_PRIVATE_IRIS_SET_CALIBRATION,
     79 	V4L2_CID_PRIVATE_IRIS_SET_SPURTABLE = 0x0098092D,
     80 	V4L2_CID_PRIVATE_IRIS_GET_SPUR_TBL  = 0x0098092E,
     81 };
     82 
     83 enum iris_evt_t {
     84 	IRIS_EVT_RADIO_READY,
     85 	IRIS_EVT_TUNE_SUCC,
     86 	IRIS_EVT_SEEK_COMPLETE,
     87 	IRIS_EVT_SCAN_NEXT,
     88 	IRIS_EVT_NEW_RAW_RDS,
     89 	IRIS_EVT_NEW_RT_RDS,
     90 	IRIS_EVT_NEW_PS_RDS,
     91 	IRIS_EVT_ERROR,
     92 	IRIS_EVT_BELOW_TH,
     93 	IRIS_EVT_ABOVE_TH,
     94 	IRIS_EVT_STEREO,
     95 	IRIS_EVT_MONO,
     96 	IRIS_EVT_RDS_AVAIL,
     97 	IRIS_EVT_RDS_NOT_AVAIL,
     98 	IRIS_EVT_NEW_SRCH_LIST,
     99 	IRIS_EVT_NEW_AF_LIST,
    100 	IRIS_EVT_TXRDSDAT,
    101 	IRIS_EVT_TXRDSDONE,
    102 	IRIS_EVT_RADIO_DISABLED,
    103 	IRIS_EVT_NEW_ODA,
    104 	IRIS_EVT_NEW_RT_PLUS,
    105 	IRIS_EVT_NEW_ERT,
    106 	IRIS_EVT_SPUR_TBL,
    107 };
    108 #endif
    109