1 ; OpenRISC 1000 architecture. -*- Scheme -*- 2 ; Copyright 2000-2014 Free Software Foundation, Inc. 3 ; Contributed for OR32 by Johan Rydberg, jrydberg (a] opencores.org 4 ; Modified by Julius Baxter, juliusbaxter (a] gmail.com 5 ; Modified by Peter Gavin, pgavin (a] gmail.com 6 ; 7 ; This program is free software; you can redistribute it and/or modify 8 ; it under the terms of the GNU General Public License as published by 9 ; the Free Software Foundation; either version 3 of the License, or 10 ; (at your option) any later version. 11 ; 12 ; This program is distributed in the hope that it will be useful, 13 ; but WITHOUT ANY WARRANTY; without even the implied warranty of 14 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 ; GNU General Public License for more details. 16 ; 17 ; You should have received a copy of the GNU General Public License 18 ; along with this program; if not, see <http://www.gnu.org/licenses/> 19 20 (include "simplify.inc") 21 22 ; The OpenRISC family is a set of RISC microprocessor architectures with an 23 ; emphasis on scalability and is targetted at embedded use. 24 ; The CPU RTL development is a collaborative open source effort. 25 ; http://opencores.org/or1k 26 ; http://openrisc.net 27 28 (define-arch 29 (name or1k) 30 (comment "OpenRISC 1000") 31 (default-alignment aligned) 32 (insn-lsb0? #t) 33 (machs or32 or32nd or64 or64nd) 34 (isas openrisc) 35 ) 36 37 ; Instruction set parameters. 38 (define-isa 39 ; Name of the ISA. 40 (name openrisc) 41 ; Base insturction length. The insns are always 32 bits wide. 42 (base-insn-bitsize 32) 43 ) 44 45 (define-pmacro OR32-MACHS or32,or32nd) 46 (define-pmacro OR64-MACHS or64,or64nd) 47 (define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd) 48 (define-pmacro ORFPX-MACHS or32,or32nd,or64,or64nd) 49 (define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd) 50 (define-pmacro ORFPX64-MACHS or64,or64nd) 51 52 (define-attr 53 (for model) 54 (type boolean) 55 (name NO-DELAY-SLOT) 56 (comment "does not have delay slots") 57 ) 58 59 (if (keep-mach? (or32 or32nd)) 60 (begin 61 (define-cpu 62 (name or1k32bf) 63 (comment "OpenRISC 1000 32-bit CPU family") 64 (insn-endian big) 65 (data-endian big) 66 (word-bitsize 32) 67 (file-transform "") 68 ) 69 70 (define-mach 71 (name or32) 72 (comment "Generic OpenRISC 1000 32-bit CPU") 73 (cpu or1k32bf) 74 (bfd-name "or1k") 75 ) 76 77 (define-mach 78 (name or32nd) 79 (comment "Generic OpenRISC 1000 32-bit CPU") 80 (cpu or1k32bf) 81 (bfd-name "or1knd") 82 ) 83 84 ; OpenRISC 1200 - 32-bit or1k CPU implementation 85 (define-model 86 (name or1200) (comment "OpenRISC 1200 model") 87 (attrs) 88 (mach or32) 89 (unit u-exec "Execution Unit" () 1 1 () () () ()) 90 ) 91 92 ; OpenRISC 1200 - 32-bit or1k CPU implementation 93 (define-model 94 (name or1200nd) (comment "OpenRISC 1200 model") 95 (attrs NO-DELAY-SLOT) 96 (mach or32nd) 97 (unit u-exec "Execution Unit" () 1 1 () () () ()) 98 ) 99 ) 100 ) 101 102 (if (keep-mach? (or64 or64nd)) 103 (begin 104 (define-cpu 105 (name or1k64bf) 106 (comment "OpenRISC 1000 64-bit CPU family") 107 (insn-endian big) 108 (data-endian big) 109 (word-bitsize 64) 110 (file-transform "64") 111 ) 112 113 (define-mach 114 (name or64) 115 (comment "Generic OpenRISC 1000 64-bit CPU") 116 (cpu or1k64bf) 117 (bfd-name "or1k64") 118 ) 119 120 (define-mach 121 (name or64nd) 122 (comment "Generic OpenRISC 1000 ND 64-bit CPU") 123 (cpu or1k64bf) 124 (bfd-name "or1k64nd") 125 ) 126 ) 127 ) 128 129 (include "or1kcommon.cpu") 130 (include "or1korbis.cpu") 131 (include "or1korfpx.cpu") 132
