Lines Matching full:dst_high
870 Register dst_high = destination.AsRegisterPairHigh<Register>();
874 __ MoveFromFpuHigh(dst_high, src);
1234 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
1245 __ And(dst_high, lhs_high, rhs_high);
1248 __ Or(dst_high, lhs_high, rhs_high);
1251 __ Xor(dst_high, lhs_high, rhs_high);
1262 __ Addu(dst_high, lhs_high, rhs_high);
1263 __ Addu(dst_high, dst_high, TMP);
1268 __ Subu(dst_high, lhs_high, rhs_high);
1269 __ Subu(dst_high, dst_high, TMP);
1285 if (dst_high != lhs_high || high != 0) {
1286 __ Ori(dst_high, lhs_high, high);
1292 __ Or(dst_high, lhs_high, TMP);
1306 if (dst_high != lhs_high || high != 0) {
1307 __ Xori(dst_high, lhs_high, high);
1313 __ Xor(dst_high, lhs_high, TMP);
1327 __ Andi(dst_high, lhs_high, high);
1332 __ And(dst_high, lhs_high, TMP);
1333 } else if (dst_high != lhs_high) {
1334 __ Move(dst_high, lhs_high);
1357 if (dst_high != lhs_high || high != 0) {
1358 __ Addiu(dst_high, lhs_high, high);
1364 __ Addu(dst_high, lhs_high, TMP);
1367 __ Addu(dst_high, dst_high, AT);
1490 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
1500 __ Srl(dst_high, lhs_low, kMipsBitsPerWord - shift_value);
1501 __ Ins(dst_high, lhs_high, shift_value, kMipsBitsPerWord - shift_value);
1506 __ Sra(dst_high, lhs_high, shift_value);
1510 __ Srl(dst_high, lhs_high, shift_value);
1514 __ Srl(dst_high, lhs_high, shift_value);
1515 __ Ins(dst_high, lhs_low, kMipsBitsPerWord - shift_value, shift_value);
1521 __ Sll(dst_high, lhs_high, shift_value);
1522 __ Or(dst_high, dst_high, TMP);
1524 __ Sra(dst_high, lhs_high, shift_value);
1529 __ Srl(dst_high, lhs_high, shift_value);
1538 __ Sll(dst_high, lhs_low, kMipsBitsPerWord - shift_value);
1539 __ Or(dst_high, dst_high, TMP);
1545 __ Sll(dst_high, lhs_low, shift_value_high);
1549 __ Sra(dst_high, dst_low, kMipsBitsPerWord - 1);
1552 __ Move(dst_high, ZERO);
1557 __ Move(dst_high, lhs_low);
1562 __ Srl(dst_high, lhs_low, shift_value_high);
1563 __ Ins(dst_high, lhs_high, kMipsBitsPerWord - shift_value_high, shift_value_high);
1569 __ Srl(dst_high, lhs_low, shift_value_high);
1570 __ Or(dst_high, dst_high, TMP);
1582 __ Sllv(dst_high, lhs_high, rhs_reg);
1583 __ Or(dst_high, dst_high, TMP);
1586 __ Move(dst_high, dst_low);
1589 __ Srav(dst_high, lhs_high, rhs_reg);
1597 __ Move(dst_low, dst_high);
1598 __ Sra(dst_high, dst_high, 31);
1600 __ Srlv(dst_high, lhs_high, rhs_reg);
1608 __ Move(dst_low, dst_high);
1609 __ Move(dst_high, ZERO);
1617 __ Sll(dst_high, lhs_low, 1);
1618 __ Sllv(dst_high, dst_high, AT);
1619 __ Or(dst_high, dst_high, TMP);
1622 __ Move(TMP, dst_high);
1623 __ Move(dst_high, dst_low);
3479 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
3481 __ LoadFromOffset(kLoadWord, dst_high, obj, offset + kMipsWordSize);
3487 __ LoadFromOffset(kLoadWord, dst_high, obj, offset + kMipsWordSize);
4145 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
4153 // The algorithm is wrong if dst_high is either lhs_lo or rhs_lo:
4155 DCHECK_NE(dst_high, lhs_low);
4156 DCHECK_NE(dst_high, rhs_low);
4165 __ MulR6(dst_high, lhs_low, rhs_high);
4166 __ Addu(dst_high, dst_high, TMP);
4168 __ Addu(dst_high, dst_high, TMP);
4172 __ MulR2(dst_high, lhs_low, rhs_high);
4173 __ Addu(dst_high, dst_high, TMP);
4176 __ Addu(dst_high, dst_high, TMP);
4231 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
4237 __ Subu(dst_high, ZERO, src_high);
4238 __ Subu(dst_high, dst_high, TMP);
4336 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
4340 __ Nor(dst_high, src_high, ZERO);
4764 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
4769 __ Sra(dst_high, src, 31);
4852 Register dst_high = locations->Out().AsRegisterPairHigh<Register>();
4903 __ LoadConst32(dst_high, std::numeric_limits<int32_t>::min());
4905 __ And(dst_high, dst_high, TMP);
4917 __ Mfhc1(dst_high, FTMP);
