Lines Matching full:srcreg
248 unsigned &SrcReg, unsigned &DstReg,
254 SrcReg = MI.getOperand(1).getReg();
816 unsigned DestReg, unsigned SrcReg,
822 PPC::VSRCRegClass.contains(SrcReg)) {
826 if (VSXSelfCopyCrash && SrcReg == SuperReg)
831 PPC::VSRCRegClass.contains(SrcReg)) {
835 if (VSXSelfCopyCrash && SrcReg == SuperReg)
839 } else if (PPC::F8RCRegClass.contains(SrcReg) &&
842 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
847 SrcReg = SuperReg;
848 } else if (PPC::VRRCRegClass.contains(SrcReg) &&
851 TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass);
856 SrcReg = SuperReg;
860 if (PPC::CRBITRCRegClass.contains(SrcReg) &&
862 unsigned CRReg = getCRFromCRBit(SrcReg);
869 .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
873 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
876 .addReg(SrcReg), getKillRegState(KillSrc);
878 } else if (PPC::CRRCRegClass.contains(SrcReg) &&
881 .addReg(SrcReg), getKillRegState(KillSrc);
886 if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
888 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
890 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
892 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
894 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
896 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg))
906 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) ||
907 PPC::VSSRCRegClass.contains(DestReg, SrcReg))
909 else if (PPC::QFRCRegClass.contains(DestReg, SrcReg))
911 else if (PPC::QSRCRegClass.contains(DestReg, SrcReg))
913 else if (PPC::QBRCRegClass.contains(DestReg, SrcReg))
915 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
923 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
925 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
931 unsigned SrcReg, bool isKill,
943 .addReg(SrcReg,
949 .addReg(SrcReg,
954 .addReg(SrcReg,
959 .addReg(SrcReg,
964 .addReg(SrcReg,
970 .addReg(SrcReg,
976 .addReg(SrcReg,
982 .addReg(SrcReg,
988 .addReg(SrcReg,
994 .addReg(SrcReg,
1002 .addReg(SrcReg,
1008 .addReg(SrcReg,
1014 .addReg(SrcReg,
1020 .addReg(SrcReg,
1034 unsigned SrcReg, bool isKill, int FrameIdx,
1044 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
1477 unsigned &SrcReg, unsigned &SrcReg2,
1487 SrcReg = MI->getOperand(1).getReg();
1498 SrcReg = MI->getOperand(1).getReg();
1505 unsigned SrcReg, unsigned SrcReg2,
1532 // Get the unique definition of SrcReg.
1533 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
1644 ((Instr.getOperand(1).getReg() == SrcReg &&
1647 Instr.getOperand(2).getReg() == SrcReg))) {
1693 Sub->getOperand(2).getReg() == SrcReg;
