| /external/llvm/lib/Target/Hexagon/ |
| HexagonSplitConst32AndConst64.cpp | 93 int DestReg = MI->getOperand(0).getReg();
97 TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
99 TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
108 int DestReg = MI->getOperand(0).getReg();
121 TII->get(Hexagon::A2_tfrsi), DestReg).addImm(ImmValue);
127 int DestReg = MI->getOperand(0).getReg();
139 unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::subreg_loreg);
140 unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::subreg_hireg);
|
| HexagonCopyToCombine.cpp | 94 void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
97 void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
100 void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
103 void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
124 unsigned DestReg = Op0.getReg();
126 return Hexagon::IntRegsRegClass.contains(DestReg) &&
137 unsigned DestReg = Op0.getReg();
146 return Hexagon::IntRegsRegClass.contains(DestReg) &&
204 /// instruction from \p UseReg to \p DestReg over the instruction \p I.
206 unsigned DestReg,
[all...] |
| HexagonVLIWPacketizer.cpp | 388 unsigned DestReg = MI->getOperand(0).getReg();
391 if (MO.isReg() && MO.getReg() == DestReg)
[all...] |
| HexagonFrameLowering.cpp | [all...] |
| HexagonInstrInfo.cpp | 597 MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg,
600 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
601 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg).addReg(SrcReg);
604 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
605 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg).addReg(SrcReg);
608 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
611 DestReg).addReg(SrcReg).addReg(SrcReg);
614 if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
617 if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
619 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrsi), (RI.getSubReg(DestReg,
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 198 unsigned DestReg = MI.getOperand(0).getReg();
199 unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
200 unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 116 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
117 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
118 VRBase = DestReg;
120 } else if (DestReg != SrcReg)
159 // Figure out the register class to create for the destreg.
479 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
480 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
481 VRBase = DestReg;
519 // Create the destreg if it is missing.
534 // Figure out the register class to create for the destreg. It should b
[all...] |
| FunctionLoweringInfo.cpp | 419 unsigned DestReg = ValueMap[PN];
420 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
422 LiveOutRegInfo.grow(DestReg);
423 LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
|
| SelectionDAGISel.cpp | 693 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
694 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
705 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600MachineScheduler.cpp | 275 unsigned DestReg = MI->getOperand(0).getReg();
276 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_XRegClass) ||
277 regBelongsToClass(DestReg, &AMDGPU::R600_AddrRegClass))
279 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_YRegClass))
281 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass))
283 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_WRegClass))
285 if (regBelongsToClass(DestReg, &AMDGPU::R600_Reg128RegClass))
364 unsigned DestReg = MI->getOperand(DstIndex).getReg();
371 MO.getReg() == DestReg)
374 // Constrains the regclass of DestReg to assign it to Slo
[all...] |
| SIFoldOperands.cpp | 245 unsigned DestReg = UseMI->getOperand(0).getReg();
247 = TargetRegisterInfo::isVirtualRegister(DestReg) ?
248 MRI.getRegClass(DestReg) :
249 TRI.getPhysRegClass(DestReg);
|
| SILoadStoreOptimizer.cpp | 246 unsigned DestReg = MRI->createVirtualRegister(SuperRC);
250 = BuildMI(*MBB, I, DL, Read2Desc, DestReg)
266 .addReg(DestReg, 0, SubRegIdx0);
269 .addReg(DestReg, RegState::Kill, SubRegIdx1);
291 LIS->createAndComputeVirtRegInterval(DestReg);
|
| /external/llvm/lib/CodeGen/ |
| PHIElimination.cpp | 234 unsigned DestReg = MPhi->getOperand(0).getReg();
251 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
263 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
267 TII->get(TargetOpcode::COPY), DestReg)
305 LV->addVirtualRegisterDead(DestReg, PHICopy);
306 LV->removeVirtualRegisterDead(DestReg, MPhi);
329 LiveInterval &DestLI = LIS->getInterval(DestReg);
344 // instruction from DestReg's live interval.
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64A57FPLoadBalancing.cpp | 627 unsigned DestReg = MI->getOperand(0).getReg();
630 << TRI->getName(DestReg) << " at " << *MI);
632 auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg));
633 ActiveChains[DestReg] = G.get();
640 unsigned DestReg = MI->getOperand(0).getReg();
645 if (DestReg != AccumReg)
660 ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg));
662 if (DestReg != AccumReg) {
663 ActiveChains[DestReg] = ActiveChains[AccumReg];
675 << TRI->getName(DestReg) << "\n")
[all...] |
| AArch64ConditionalCompares.cpp | 595 unsigned DestReg =
599 .addReg(DestReg, RegState::Define | RegState::Dead)
|
| AArch64LoadStoreOptimizer.cpp | [all...] |
| AArch64FastISel.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 510 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset>
523 unsigned DestReg = MI.getOperand(0).getReg();
524 assert(MI.definesRegister(DestReg) &&
532 if (DestReg != PPC::CR0) {
536 unsigned ShiftBits = getEncodingValue(DestReg)*4;
543 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
597 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset>
610 unsigned DestReg = MI.getOperand(0).getReg();
611 assert(MI.definesRegister(DestReg) &&
617 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
[all...] |
| PPCFastISel.cpp | 155 bool isZExt, unsigned DestReg);
164 unsigned DestReg, bool IsZExt);
801 bool IsZExt, unsigned DestReg) {
885 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
888 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
926 unsigned DestReg = createResultReg(&PPC::F4RCRegClass);
927 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP), DestReg)
930 updateValueMap(I, DestReg);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 850 unsigned RdhwrOpc, DestReg;
854 DestReg = Mips::V1;
857 DestReg = Mips::V1_64;
864 SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
866 SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
[all...] |
| MipsFastISel.cpp | 119 bool emitCmp(unsigned DestReg, const CmpInst *CI);
127 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
130 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
132 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
134 unsigned DestReg);
136 unsigned DestReg);
334 unsigned DestReg = createResultReg(RC);
336 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
337 return DestReg;
340 unsigned DestReg = createResultReg(RC)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 125 unsigned DestReg = MI->getOperand(0).getReg();
127 bool DestIsHigh = isHighReg(DestReg);
133 DestReg, SrcReg, SystemZ::LR, 32,
136 MI->getOperand(1).setReg(DestReg);
164 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
170 DebugLoc DL, unsigned DestReg,
174 bool DestIsHigh = isHighReg(DestReg);
183 BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
188 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FloatingPoint.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 661 unsigned DestReg, bool KillSrc,
668 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
704 unsigned DestReg, unsigned SrcReg,
706 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
710 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
715 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
725 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP())
727 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
731 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
745 if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
[all...] |
| ARMFastISel.cpp | 482 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
484 TII.get(Opc), DestReg).addImm(Imm));
485 return DestReg;
498 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
503 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
506 return DestReg;
587 unsigned DestReg = createResultReg(RC);
612 TII.get(Opc), DestReg).addGlobalAddress(GV, 0, TF));
638 DestReg).addConstantPoolIndex(Idx);
644 DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0)
[all...] |
