1 /****************************************************************************** 2 * 3 * Copyright (C) 2015 The Android Open Source Project 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ***************************************************************************** 18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19 */ 20 21 /*****************************************************************************/ 22 /* */ 23 /* File Name : ih264d_api.c */ 24 /* */ 25 /* Description : Has all API related functions */ 26 /* */ 27 /* */ 28 /* List of Functions : api_check_struct_sanity */ 29 /* ih264d_set_processor */ 30 /* ih264d_create */ 31 /* ih264d_delete */ 32 /* ih264d_init */ 33 /* ih264d_map_error */ 34 /* ih264d_video_decode */ 35 /* ih264d_get_version */ 36 /* ih264d_get_display_frame */ 37 /* ih264d_set_display_frame */ 38 /* ih264d_set_flush_mode */ 39 /* ih264d_get_status */ 40 /* ih264d_get_buf_info */ 41 /* ih264d_set_params */ 42 /* ih264d_set_default_params */ 43 /* ih264d_reset */ 44 /* ih264d_ctl */ 45 /* ih264d_rel_display_frame */ 46 /* ih264d_set_degrade */ 47 /* ih264d_get_frame_dimensions */ 48 /* ih264d_set_num_cores */ 49 /* ih264d_fill_output_struct_from_context */ 50 /* ih264d_api_function */ 51 /* */ 52 /* Issues / Problems : None */ 53 /* */ 54 /* Revision History : */ 55 /* */ 56 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 57 /* 14 10 2008 100356(SKV) Draft */ 58 /* */ 59 /*****************************************************************************/ 60 #include "ih264_typedefs.h" 61 #include "ih264_macros.h" 62 #include "ih264_platform_macros.h" 63 #include "ih264d_tables.h" 64 #include "iv.h" 65 #include "ivd.h" 66 #include "ih264d.h" 67 #include "ih264d_defs.h" 68 69 #include <string.h> 70 #include <limits.h> 71 #include <stddef.h> 72 73 #include "ih264d_inter_pred.h" 74 75 #include "ih264d_structs.h" 76 #include "ih264d_nal.h" 77 #include "ih264d_error_handler.h" 78 79 #include "ih264d_defs.h" 80 81 #include "ithread.h" 82 #include "ih264d_parse_slice.h" 83 #include "ih264d_function_selector.h" 84 #include "ih264_error.h" 85 #include "ih264_disp_mgr.h" 86 #include "ih264_buf_mgr.h" 87 #include "ih264d_deblocking.h" 88 #include "ih264d_parse_cavlc.h" 89 #include "ih264d_parse_cabac.h" 90 #include "ih264d_utils.h" 91 #include "ih264d_format_conv.h" 92 #include "ih264d_parse_headers.h" 93 #include "ih264d_thread_compute_bs.h" 94 #include <assert.h> 95 96 97 /*********************/ 98 /* Codec Versioning */ 99 /*********************/ 100 //Move this to where it is used 101 #define CODEC_NAME "H264VDEC" 102 #define CODEC_RELEASE_TYPE "production" 103 #define CODEC_RELEASE_VER "05.00" 104 #define CODEC_VENDOR "ITTIAM" 105 #define MAXVERSION_STRLEN 511 106 #ifdef __ANDROID__ 107 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \ 108 snprintf(version_string, MAXVERSION_STRLEN, \ 109 "@(#)Id:%s_%s Ver:%s Released by %s", \ 110 codec_name, codec_release_type, codec_release_ver, codec_vendor) 111 #else 112 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \ 113 snprintf(version_string, MAXVERSION_STRLEN, \ 114 "@(#)Id:%s_%s Ver:%s Released by %s Build: %s @ %s", \ 115 codec_name, codec_release_type, codec_release_ver, codec_vendor, __DATE__, __TIME__) 116 #endif 117 118 119 #define MIN_IN_BUFS 1 120 #define MIN_OUT_BUFS_420 3 121 #define MIN_OUT_BUFS_422ILE 1 122 #define MIN_OUT_BUFS_RGB565 1 123 #define MIN_OUT_BUFS_420SP 2 124 125 #define NUM_FRAMES_LIMIT_ENABLED 0 126 127 #if NUM_FRAMES_LIMIT_ENABLED 128 #define NUM_FRAMES_LIMIT 10000 129 #else 130 #define NUM_FRAMES_LIMIT 0x7FFFFFFF 131 #endif 132 133 134 UWORD32 ih264d_get_extra_mem_external(UWORD32 width, UWORD32 height); 135 WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl, 136 void *pv_api_ip, 137 void *pv_api_op); 138 WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl, 139 void *pv_api_ip, 140 void *pv_api_op); 141 142 WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op); 143 144 WORD32 ih264d_deblock_display(dec_struct_t *ps_dec); 145 146 void ih264d_signal_decode_thread(dec_struct_t *ps_dec); 147 148 void ih264d_signal_bs_deblk_thread(dec_struct_t *ps_dec); 149 void ih264d_decode_picture_thread(dec_struct_t *ps_dec); 150 151 WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj, 152 void *pv_api_ip, 153 void *pv_api_op); 154 155 void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec, 156 ivd_video_decode_op_t *ps_dec_op); 157 158 static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle, 159 void *pv_api_ip, 160 void *pv_api_op) 161 { 162 IVD_API_COMMAND_TYPE_T e_cmd; 163 UWORD32 *pu4_api_ip; 164 UWORD32 *pu4_api_op; 165 UWORD32 i, j; 166 167 if(NULL == pv_api_op) 168 return (IV_FAIL); 169 170 if(NULL == pv_api_ip) 171 return (IV_FAIL); 172 173 pu4_api_ip = (UWORD32 *)pv_api_ip; 174 pu4_api_op = (UWORD32 *)pv_api_op; 175 e_cmd = *(pu4_api_ip + 1); 176 177 /* error checks on handle */ 178 switch((WORD32)e_cmd) 179 { 180 case IVD_CMD_CREATE: 181 break; 182 183 case IVD_CMD_REL_DISPLAY_FRAME: 184 case IVD_CMD_SET_DISPLAY_FRAME: 185 case IVD_CMD_GET_DISPLAY_FRAME: 186 case IVD_CMD_VIDEO_DECODE: 187 case IVD_CMD_DELETE: 188 case IVD_CMD_VIDEO_CTL: 189 if(ps_handle == NULL) 190 { 191 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 192 *(pu4_api_op + 1) |= IVD_HANDLE_NULL; 193 return IV_FAIL; 194 } 195 196 if(ps_handle->u4_size != sizeof(iv_obj_t)) 197 { 198 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 199 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT; 200 return IV_FAIL; 201 } 202 203 if(ps_handle->pv_fxns != ih264d_api_function) 204 { 205 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 206 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 207 return IV_FAIL; 208 } 209 210 if(ps_handle->pv_codec_handle == NULL) 211 { 212 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 213 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL; 214 return IV_FAIL; 215 } 216 break; 217 default: 218 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 219 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD; 220 return IV_FAIL; 221 } 222 223 switch((WORD32)e_cmd) 224 { 225 case IVD_CMD_CREATE: 226 { 227 ih264d_create_ip_t *ps_ip = (ih264d_create_ip_t *)pv_api_ip; 228 ih264d_create_op_t *ps_op = (ih264d_create_op_t *)pv_api_op; 229 230 231 ps_op->s_ivd_create_op_t.u4_error_code = 0; 232 233 if((ps_ip->s_ivd_create_ip_t.u4_size > sizeof(ih264d_create_ip_t)) 234 || (ps_ip->s_ivd_create_ip_t.u4_size 235 < sizeof(ivd_create_ip_t))) 236 { 237 ps_op->s_ivd_create_op_t.u4_error_code |= 1 238 << IVD_UNSUPPORTEDPARAM; 239 ps_op->s_ivd_create_op_t.u4_error_code |= 240 IVD_IP_API_STRUCT_SIZE_INCORRECT; 241 H264_DEC_DEBUG_PRINT("\n"); 242 return (IV_FAIL); 243 } 244 245 if((ps_op->s_ivd_create_op_t.u4_size != sizeof(ih264d_create_op_t)) 246 && (ps_op->s_ivd_create_op_t.u4_size 247 != sizeof(ivd_create_op_t))) 248 { 249 ps_op->s_ivd_create_op_t.u4_error_code |= 1 250 << IVD_UNSUPPORTEDPARAM; 251 ps_op->s_ivd_create_op_t.u4_error_code |= 252 IVD_OP_API_STRUCT_SIZE_INCORRECT; 253 H264_DEC_DEBUG_PRINT("\n"); 254 return (IV_FAIL); 255 } 256 257 258 if((ps_ip->s_ivd_create_ip_t.e_output_format != IV_YUV_420P) 259 && (ps_ip->s_ivd_create_ip_t.e_output_format 260 != IV_YUV_422ILE) 261 && (ps_ip->s_ivd_create_ip_t.e_output_format 262 != IV_RGB_565) 263 && (ps_ip->s_ivd_create_ip_t.e_output_format 264 != IV_YUV_420SP_UV) 265 && (ps_ip->s_ivd_create_ip_t.e_output_format 266 != IV_YUV_420SP_VU)) 267 { 268 ps_op->s_ivd_create_op_t.u4_error_code |= 1 269 << IVD_UNSUPPORTEDPARAM; 270 ps_op->s_ivd_create_op_t.u4_error_code |= 271 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED; 272 H264_DEC_DEBUG_PRINT("\n"); 273 return (IV_FAIL); 274 } 275 276 } 277 break; 278 279 case IVD_CMD_GET_DISPLAY_FRAME: 280 { 281 ih264d_get_display_frame_ip_t *ps_ip = 282 (ih264d_get_display_frame_ip_t *)pv_api_ip; 283 ih264d_get_display_frame_op_t *ps_op = 284 (ih264d_get_display_frame_op_t *)pv_api_op; 285 286 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0; 287 288 if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size 289 != sizeof(ih264d_get_display_frame_ip_t)) 290 && (ps_ip->s_ivd_get_display_frame_ip_t.u4_size 291 != sizeof(ivd_get_display_frame_ip_t))) 292 { 293 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 294 << IVD_UNSUPPORTEDPARAM; 295 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 296 IVD_IP_API_STRUCT_SIZE_INCORRECT; 297 return (IV_FAIL); 298 } 299 300 if((ps_op->s_ivd_get_display_frame_op_t.u4_size 301 != sizeof(ih264d_get_display_frame_op_t)) 302 && (ps_op->s_ivd_get_display_frame_op_t.u4_size 303 != sizeof(ivd_get_display_frame_op_t))) 304 { 305 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 306 << IVD_UNSUPPORTEDPARAM; 307 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 308 IVD_OP_API_STRUCT_SIZE_INCORRECT; 309 return (IV_FAIL); 310 } 311 } 312 break; 313 314 case IVD_CMD_REL_DISPLAY_FRAME: 315 { 316 ih264d_rel_display_frame_ip_t *ps_ip = 317 (ih264d_rel_display_frame_ip_t *)pv_api_ip; 318 ih264d_rel_display_frame_op_t *ps_op = 319 (ih264d_rel_display_frame_op_t *)pv_api_op; 320 321 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0; 322 323 if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size 324 != sizeof(ih264d_rel_display_frame_ip_t)) 325 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size 326 != sizeof(ivd_rel_display_frame_ip_t))) 327 { 328 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 329 << IVD_UNSUPPORTEDPARAM; 330 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 331 IVD_IP_API_STRUCT_SIZE_INCORRECT; 332 return (IV_FAIL); 333 } 334 335 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size 336 != sizeof(ih264d_rel_display_frame_op_t)) 337 && (ps_op->s_ivd_rel_display_frame_op_t.u4_size 338 != sizeof(ivd_rel_display_frame_op_t))) 339 { 340 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 341 << IVD_UNSUPPORTEDPARAM; 342 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 343 IVD_OP_API_STRUCT_SIZE_INCORRECT; 344 return (IV_FAIL); 345 } 346 347 } 348 break; 349 350 case IVD_CMD_SET_DISPLAY_FRAME: 351 { 352 ih264d_set_display_frame_ip_t *ps_ip = 353 (ih264d_set_display_frame_ip_t *)pv_api_ip; 354 ih264d_set_display_frame_op_t *ps_op = 355 (ih264d_set_display_frame_op_t *)pv_api_op; 356 UWORD32 j; 357 358 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0; 359 360 if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size 361 != sizeof(ih264d_set_display_frame_ip_t)) 362 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size 363 != sizeof(ivd_set_display_frame_ip_t))) 364 { 365 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 366 << IVD_UNSUPPORTEDPARAM; 367 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 368 IVD_IP_API_STRUCT_SIZE_INCORRECT; 369 return (IV_FAIL); 370 } 371 372 if((ps_op->s_ivd_set_display_frame_op_t.u4_size 373 != sizeof(ih264d_set_display_frame_op_t)) 374 && (ps_op->s_ivd_set_display_frame_op_t.u4_size 375 != sizeof(ivd_set_display_frame_op_t))) 376 { 377 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 378 << IVD_UNSUPPORTEDPARAM; 379 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 380 IVD_OP_API_STRUCT_SIZE_INCORRECT; 381 return (IV_FAIL); 382 } 383 384 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0) 385 { 386 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 387 << IVD_UNSUPPORTEDPARAM; 388 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 389 IVD_DISP_FRM_ZERO_OP_BUFS; 390 return IV_FAIL; 391 } 392 393 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs; 394 j++) 395 { 396 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs 397 == 0) 398 { 399 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 400 << IVD_UNSUPPORTEDPARAM; 401 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 402 IVD_DISP_FRM_ZERO_OP_BUFS; 403 return IV_FAIL; 404 } 405 406 for(i = 0; 407 i 408 < ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs; 409 i++) 410 { 411 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i] 412 == NULL) 413 { 414 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 415 << IVD_UNSUPPORTEDPARAM; 416 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 417 IVD_DISP_FRM_OP_BUF_NULL; 418 return IV_FAIL; 419 } 420 421 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i] 422 == 0) 423 { 424 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 425 << IVD_UNSUPPORTEDPARAM; 426 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 427 IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 428 return IV_FAIL; 429 } 430 } 431 } 432 } 433 break; 434 435 case IVD_CMD_VIDEO_DECODE: 436 { 437 ih264d_video_decode_ip_t *ps_ip = 438 (ih264d_video_decode_ip_t *)pv_api_ip; 439 ih264d_video_decode_op_t *ps_op = 440 (ih264d_video_decode_op_t *)pv_api_op; 441 442 H264_DEC_DEBUG_PRINT("The input bytes is: %d", 443 ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes); 444 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0; 445 446 if(ps_ip->s_ivd_video_decode_ip_t.u4_size 447 != sizeof(ih264d_video_decode_ip_t)&& 448 ps_ip->s_ivd_video_decode_ip_t.u4_size != offsetof(ivd_video_decode_ip_t, s_out_buffer)) 449 { 450 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 451 << IVD_UNSUPPORTEDPARAM; 452 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 453 IVD_IP_API_STRUCT_SIZE_INCORRECT; 454 return (IV_FAIL); 455 } 456 457 if(ps_op->s_ivd_video_decode_op_t.u4_size 458 != sizeof(ih264d_video_decode_op_t)&& 459 ps_op->s_ivd_video_decode_op_t.u4_size != offsetof(ivd_video_decode_op_t, u4_output_present)) 460 { 461 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 462 << IVD_UNSUPPORTEDPARAM; 463 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 464 IVD_OP_API_STRUCT_SIZE_INCORRECT; 465 return (IV_FAIL); 466 } 467 468 } 469 break; 470 471 case IVD_CMD_DELETE: 472 { 473 ih264d_delete_ip_t *ps_ip = 474 (ih264d_delete_ip_t *)pv_api_ip; 475 ih264d_delete_op_t *ps_op = 476 (ih264d_delete_op_t *)pv_api_op; 477 478 ps_op->s_ivd_delete_op_t.u4_error_code = 0; 479 480 if(ps_ip->s_ivd_delete_ip_t.u4_size 481 != sizeof(ih264d_delete_ip_t)) 482 { 483 ps_op->s_ivd_delete_op_t.u4_error_code |= 1 484 << IVD_UNSUPPORTEDPARAM; 485 ps_op->s_ivd_delete_op_t.u4_error_code |= 486 IVD_IP_API_STRUCT_SIZE_INCORRECT; 487 return (IV_FAIL); 488 } 489 490 if(ps_op->s_ivd_delete_op_t.u4_size 491 != sizeof(ih264d_delete_op_t)) 492 { 493 ps_op->s_ivd_delete_op_t.u4_error_code |= 1 494 << IVD_UNSUPPORTEDPARAM; 495 ps_op->s_ivd_delete_op_t.u4_error_code |= 496 IVD_OP_API_STRUCT_SIZE_INCORRECT; 497 return (IV_FAIL); 498 } 499 500 } 501 break; 502 503 case IVD_CMD_VIDEO_CTL: 504 { 505 UWORD32 *pu4_ptr_cmd; 506 UWORD32 sub_command; 507 508 pu4_ptr_cmd = (UWORD32 *)pv_api_ip; 509 pu4_ptr_cmd += 2; 510 sub_command = *pu4_ptr_cmd; 511 512 switch(sub_command) 513 { 514 case IVD_CMD_CTL_SETPARAMS: 515 { 516 ih264d_ctl_set_config_ip_t *ps_ip; 517 ih264d_ctl_set_config_op_t *ps_op; 518 ps_ip = (ih264d_ctl_set_config_ip_t *)pv_api_ip; 519 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op; 520 521 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size 522 != sizeof(ih264d_ctl_set_config_ip_t)) 523 { 524 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 525 << IVD_UNSUPPORTEDPARAM; 526 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 527 IVD_IP_API_STRUCT_SIZE_INCORRECT; 528 return IV_FAIL; 529 } 530 } 531 //no break; is needed here 532 case IVD_CMD_CTL_SETDEFAULT: 533 { 534 ih264d_ctl_set_config_op_t *ps_op; 535 ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op; 536 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size 537 != sizeof(ih264d_ctl_set_config_op_t)) 538 { 539 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 540 << IVD_UNSUPPORTEDPARAM; 541 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 542 IVD_OP_API_STRUCT_SIZE_INCORRECT; 543 return IV_FAIL; 544 } 545 } 546 break; 547 548 case IVD_CMD_CTL_GETPARAMS: 549 { 550 ih264d_ctl_getstatus_ip_t *ps_ip; 551 ih264d_ctl_getstatus_op_t *ps_op; 552 553 ps_ip = (ih264d_ctl_getstatus_ip_t *)pv_api_ip; 554 ps_op = (ih264d_ctl_getstatus_op_t *)pv_api_op; 555 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size 556 != sizeof(ih264d_ctl_getstatus_ip_t)) 557 { 558 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 559 << IVD_UNSUPPORTEDPARAM; 560 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 561 IVD_IP_API_STRUCT_SIZE_INCORRECT; 562 return IV_FAIL; 563 } 564 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size 565 != sizeof(ih264d_ctl_getstatus_op_t)) 566 { 567 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 568 << IVD_UNSUPPORTEDPARAM; 569 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 570 IVD_OP_API_STRUCT_SIZE_INCORRECT; 571 return IV_FAIL; 572 } 573 } 574 break; 575 576 case IVD_CMD_CTL_GETBUFINFO: 577 { 578 ih264d_ctl_getbufinfo_ip_t *ps_ip; 579 ih264d_ctl_getbufinfo_op_t *ps_op; 580 ps_ip = (ih264d_ctl_getbufinfo_ip_t *)pv_api_ip; 581 ps_op = (ih264d_ctl_getbufinfo_op_t *)pv_api_op; 582 583 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size 584 != sizeof(ih264d_ctl_getbufinfo_ip_t)) 585 { 586 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 587 << IVD_UNSUPPORTEDPARAM; 588 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 589 IVD_IP_API_STRUCT_SIZE_INCORRECT; 590 return IV_FAIL; 591 } 592 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size 593 != sizeof(ih264d_ctl_getbufinfo_op_t)) 594 { 595 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 596 << IVD_UNSUPPORTEDPARAM; 597 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 598 IVD_OP_API_STRUCT_SIZE_INCORRECT; 599 return IV_FAIL; 600 } 601 } 602 break; 603 604 case IVD_CMD_CTL_GETVERSION: 605 { 606 ih264d_ctl_getversioninfo_ip_t *ps_ip; 607 ih264d_ctl_getversioninfo_op_t *ps_op; 608 ps_ip = (ih264d_ctl_getversioninfo_ip_t *)pv_api_ip; 609 ps_op = (ih264d_ctl_getversioninfo_op_t *)pv_api_op; 610 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size 611 != sizeof(ih264d_ctl_getversioninfo_ip_t)) 612 { 613 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 614 << IVD_UNSUPPORTEDPARAM; 615 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 616 IVD_IP_API_STRUCT_SIZE_INCORRECT; 617 return IV_FAIL; 618 } 619 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size 620 != sizeof(ih264d_ctl_getversioninfo_op_t)) 621 { 622 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 623 << IVD_UNSUPPORTEDPARAM; 624 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 625 IVD_OP_API_STRUCT_SIZE_INCORRECT; 626 return IV_FAIL; 627 } 628 } 629 break; 630 631 case IVD_CMD_CTL_FLUSH: 632 { 633 ih264d_ctl_flush_ip_t *ps_ip; 634 ih264d_ctl_flush_op_t *ps_op; 635 ps_ip = (ih264d_ctl_flush_ip_t *)pv_api_ip; 636 ps_op = (ih264d_ctl_flush_op_t *)pv_api_op; 637 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size 638 != sizeof(ih264d_ctl_flush_ip_t)) 639 { 640 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 641 << IVD_UNSUPPORTEDPARAM; 642 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 643 IVD_IP_API_STRUCT_SIZE_INCORRECT; 644 return IV_FAIL; 645 } 646 if(ps_op->s_ivd_ctl_flush_op_t.u4_size 647 != sizeof(ih264d_ctl_flush_op_t)) 648 { 649 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 650 << IVD_UNSUPPORTEDPARAM; 651 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 652 IVD_OP_API_STRUCT_SIZE_INCORRECT; 653 return IV_FAIL; 654 } 655 } 656 break; 657 658 case IVD_CMD_CTL_RESET: 659 { 660 ih264d_ctl_reset_ip_t *ps_ip; 661 ih264d_ctl_reset_op_t *ps_op; 662 ps_ip = (ih264d_ctl_reset_ip_t *)pv_api_ip; 663 ps_op = (ih264d_ctl_reset_op_t *)pv_api_op; 664 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size 665 != sizeof(ih264d_ctl_reset_ip_t)) 666 { 667 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 668 << IVD_UNSUPPORTEDPARAM; 669 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 670 IVD_IP_API_STRUCT_SIZE_INCORRECT; 671 return IV_FAIL; 672 } 673 if(ps_op->s_ivd_ctl_reset_op_t.u4_size 674 != sizeof(ih264d_ctl_reset_op_t)) 675 { 676 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 677 << IVD_UNSUPPORTEDPARAM; 678 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 679 IVD_OP_API_STRUCT_SIZE_INCORRECT; 680 return IV_FAIL; 681 } 682 } 683 break; 684 685 case IH264D_CMD_CTL_DEGRADE: 686 { 687 ih264d_ctl_degrade_ip_t *ps_ip; 688 ih264d_ctl_degrade_op_t *ps_op; 689 690 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip; 691 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op; 692 693 if(ps_ip->u4_size != sizeof(ih264d_ctl_degrade_ip_t)) 694 { 695 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 696 ps_op->u4_error_code |= 697 IVD_IP_API_STRUCT_SIZE_INCORRECT; 698 return IV_FAIL; 699 } 700 701 if(ps_op->u4_size != sizeof(ih264d_ctl_degrade_op_t)) 702 { 703 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 704 ps_op->u4_error_code |= 705 IVD_OP_API_STRUCT_SIZE_INCORRECT; 706 return IV_FAIL; 707 } 708 709 if((ps_ip->i4_degrade_pics < 0) 710 || (ps_ip->i4_degrade_pics > 4) 711 || (ps_ip->i4_nondegrade_interval < 0) 712 || (ps_ip->i4_degrade_type < 0) 713 || (ps_ip->i4_degrade_type > 15)) 714 { 715 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 716 return IV_FAIL; 717 } 718 719 break; 720 } 721 722 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS: 723 { 724 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip; 725 ih264d_ctl_get_frame_dimensions_op_t *ps_op; 726 727 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 728 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op; 729 730 if(ps_ip->u4_size 731 != sizeof(ih264d_ctl_get_frame_dimensions_ip_t)) 732 { 733 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 734 ps_op->u4_error_code |= 735 IVD_IP_API_STRUCT_SIZE_INCORRECT; 736 return IV_FAIL; 737 } 738 739 if(ps_op->u4_size 740 != sizeof(ih264d_ctl_get_frame_dimensions_op_t)) 741 { 742 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 743 ps_op->u4_error_code |= 744 IVD_OP_API_STRUCT_SIZE_INCORRECT; 745 return IV_FAIL; 746 } 747 748 break; 749 } 750 case IH264D_CMD_CTL_GET_VUI_PARAMS: 751 { 752 ih264d_ctl_get_vui_params_ip_t *ps_ip; 753 ih264d_ctl_get_vui_params_op_t *ps_op; 754 755 ps_ip = 756 (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip; 757 ps_op = 758 (ih264d_ctl_get_vui_params_op_t *)pv_api_op; 759 760 if(ps_ip->u4_size 761 != sizeof(ih264d_ctl_get_vui_params_ip_t)) 762 { 763 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 764 ps_op->u4_error_code |= 765 IVD_IP_API_STRUCT_SIZE_INCORRECT; 766 return IV_FAIL; 767 } 768 769 if(ps_op->u4_size 770 != sizeof(ih264d_ctl_get_vui_params_op_t)) 771 { 772 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 773 ps_op->u4_error_code |= 774 IVD_OP_API_STRUCT_SIZE_INCORRECT; 775 return IV_FAIL; 776 } 777 778 break; 779 } 780 case IH264D_CMD_CTL_SET_NUM_CORES: 781 { 782 ih264d_ctl_set_num_cores_ip_t *ps_ip; 783 ih264d_ctl_set_num_cores_op_t *ps_op; 784 785 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip; 786 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op; 787 788 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_num_cores_ip_t)) 789 { 790 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 791 ps_op->u4_error_code |= 792 IVD_IP_API_STRUCT_SIZE_INCORRECT; 793 return IV_FAIL; 794 } 795 796 if(ps_op->u4_size != sizeof(ih264d_ctl_set_num_cores_op_t)) 797 { 798 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 799 ps_op->u4_error_code |= 800 IVD_OP_API_STRUCT_SIZE_INCORRECT; 801 return IV_FAIL; 802 } 803 804 if((ps_ip->u4_num_cores != 1) && (ps_ip->u4_num_cores != 2) 805 && (ps_ip->u4_num_cores != 3) 806 && (ps_ip->u4_num_cores != 4)) 807 { 808 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 809 return IV_FAIL; 810 } 811 break; 812 } 813 case IH264D_CMD_CTL_SET_PROCESSOR: 814 { 815 ih264d_ctl_set_processor_ip_t *ps_ip; 816 ih264d_ctl_set_processor_op_t *ps_op; 817 818 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip; 819 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op; 820 821 if(ps_ip->u4_size != sizeof(ih264d_ctl_set_processor_ip_t)) 822 { 823 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 824 ps_op->u4_error_code |= 825 IVD_IP_API_STRUCT_SIZE_INCORRECT; 826 return IV_FAIL; 827 } 828 829 if(ps_op->u4_size != sizeof(ih264d_ctl_set_processor_op_t)) 830 { 831 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 832 ps_op->u4_error_code |= 833 IVD_OP_API_STRUCT_SIZE_INCORRECT; 834 return IV_FAIL; 835 } 836 837 break; 838 } 839 default: 840 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM; 841 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD; 842 return IV_FAIL; 843 break; 844 } 845 } 846 break; 847 } 848 849 return IV_SUCCESS; 850 } 851 852 853 /** 854 ******************************************************************************* 855 * 856 * @brief 857 * Sets Processor type 858 * 859 * @par Description: 860 * Sets Processor type 861 * 862 * @param[in] ps_codec_obj 863 * Pointer to codec object at API level 864 * 865 * @param[in] pv_api_ip 866 * Pointer to input argument structure 867 * 868 * @param[out] pv_api_op 869 * Pointer to output argument structure 870 * 871 * @returns Status 872 * 873 * @remarks 874 * 875 * 876 ******************************************************************************* 877 */ 878 879 WORD32 ih264d_set_processor(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 880 { 881 ih264d_ctl_set_processor_ip_t *ps_ip; 882 ih264d_ctl_set_processor_op_t *ps_op; 883 dec_struct_t *ps_codec = (dec_struct_t *)dec_hdl->pv_codec_handle; 884 885 ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip; 886 ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op; 887 888 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch; 889 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc; 890 891 ih264d_init_function_ptr(ps_codec); 892 893 ps_op->u4_error_code = 0; 894 return IV_SUCCESS; 895 } 896 897 898 /************************************************************************** 899 * \if Function name : ih264d_init_decoder \endif 900 * 901 * 902 * \brief 903 * Initializes the decoder 904 * 905 * \param apiVersion : Version of the api being used. 906 * \param errorHandlingMechanism : Mechanism to be used for errror handling. 907 * \param postFilteringType: Type of post filtering operation to be used. 908 * \param uc_outputFormat: Format of the decoded picture [default 4:2:0]. 909 * \param uc_dispBufs: Number of Display Buffers. 910 * \param p_NALBufAPI: Pointer to NAL Buffer API. 911 * \param p_DispBufAPI: Pointer to Display Buffer API. 912 * \param ih264d_dec_mem_manager :Pointer to the function that will be called by decoder 913 * for memory allocation and freeing. 914 * 915 * \return 916 * 0 on Success and -1 on error 917 * 918 ************************************************************************** 919 */ 920 void ih264d_init_decoder(void * ps_dec_params) 921 { 922 dec_struct_t * ps_dec = (dec_struct_t *)ps_dec_params; 923 dec_slice_params_t *ps_cur_slice; 924 pocstruct_t *ps_prev_poc, *ps_cur_poc; 925 WORD32 size; 926 927 size = sizeof(pred_info_t) * 2 * 32; 928 memset(ps_dec->ps_pred, 0 , size); 929 930 size = sizeof(disp_mgr_t); 931 memset(ps_dec->pv_disp_buf_mgr, 0 , size); 932 933 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 934 memset(ps_dec->pv_pic_buf_mgr, 0, size); 935 936 size = sizeof(dec_err_status_t); 937 memset(ps_dec->ps_dec_err_status, 0, size); 938 939 size = sizeof(sei); 940 memset(ps_dec->ps_sei, 0, size); 941 942 size = sizeof(dpb_commands_t); 943 memset(ps_dec->ps_dpb_cmds, 0, size); 944 945 size = sizeof(dec_bit_stream_t); 946 memset(ps_dec->ps_bitstrm, 0, size); 947 948 size = sizeof(dec_slice_params_t); 949 memset(ps_dec->ps_cur_slice, 0, size); 950 951 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t)); 952 memset(ps_dec->pv_scratch_sps_pps, 0, size); 953 954 size = sizeof(ctxt_inc_mb_info_t); 955 memset(ps_dec->ps_left_mb_ctxt_info, 0, size); 956 957 size = (sizeof(neighbouradd_t) << 2); 958 memset(ps_dec->ps_left_mvpred_addr, 0 ,size); 959 960 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 961 memset(ps_dec->pv_mv_buf_mgr, 0, size); 962 963 /* Free any dynamic buffers that are allocated */ 964 ih264d_free_dynamic_bufs(ps_dec); 965 966 ps_cur_slice = ps_dec->ps_cur_slice; 967 ps_dec->init_done = 0; 968 969 ps_dec->u4_num_cores = 1; 970 971 ps_dec->u2_pic_ht = ps_dec->u2_pic_wd = 0; 972 973 ps_dec->u1_separate_parse = DEFAULT_SEPARATE_PARSE; 974 ps_dec->u4_app_disable_deblk_frm = 0; 975 ps_dec->i4_degrade_type = 0; 976 ps_dec->i4_degrade_pics = 0; 977 978 ps_dec->i4_app_skip_mode = IVD_SKIP_NONE; 979 ps_dec->i4_dec_skip_mode = IVD_SKIP_NONE; 980 981 memset(ps_dec->ps_pps, 0, 982 ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS)); 983 memset(ps_dec->ps_sps, 0, 984 ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS)); 985 986 /* Initialization of function pointers ih264d_deblock_picture function*/ 987 988 ps_dec->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff; 989 ps_dec->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff; 990 991 ps_dec->s_cab_dec_env.pv_codec_handle = ps_dec; 992 993 ps_dec->u4_num_fld_in_frm = 0; 994 995 ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec; 996 997 /* Initialize the sei validity u4_flag with zero indiacting sei is not valid*/ 998 ps_dec->ps_sei->u1_is_valid = 0; 999 1000 /* decParams Initializations */ 1001 ps_dec->ps_cur_pps = NULL; 1002 ps_dec->ps_cur_sps = NULL; 1003 ps_dec->u1_init_dec_flag = 0; 1004 ps_dec->u1_first_slice_in_stream = 1; 1005 ps_dec->u1_first_pb_nal_in_pic = 1; 1006 ps_dec->u1_last_pic_not_decoded = 0; 1007 ps_dec->u4_app_disp_width = 0; 1008 ps_dec->i4_header_decoded = 0; 1009 ps_dec->u4_total_frames_decoded = 0; 1010 1011 ps_dec->i4_error_code = 0; 1012 ps_dec->i4_content_type = -1; 1013 ps_dec->ps_cur_slice->u1_mbaff_frame_flag = 0; 1014 1015 ps_dec->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS; //REJECT_PB_PICS; 1016 ps_dec->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN; 1017 ps_dec->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT; 1018 ps_dec->ps_dec_err_status->u4_cur_frm = INIT_FRAME; 1019 ps_dec->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN; 1020 1021 ps_dec->u1_pr_sl_type = 0xFF; 1022 ps_dec->u2_mbx = 0xffff; 1023 ps_dec->u2_mby = 0; 1024 ps_dec->u2_total_mbs_coded = 0; 1025 1026 /* POC initializations */ 1027 ps_prev_poc = &ps_dec->s_prev_pic_poc; 1028 ps_cur_poc = &ps_dec->s_cur_pic_poc; 1029 ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0; 1030 ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0; 1031 ps_prev_poc->i4_delta_pic_order_cnt_bottom = 1032 ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0; 1033 ps_prev_poc->i4_delta_pic_order_cnt[0] = 1034 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0; 1035 ps_prev_poc->i4_delta_pic_order_cnt[1] = 1036 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0; 1037 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0; 1038 ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count = 1039 0; 1040 ps_prev_poc->i4_bottom_field_order_count = 1041 ps_cur_poc->i4_bottom_field_order_count = 0; 1042 ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0; 1043 ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0; 1044 ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0; 1045 ps_cur_slice->u1_mmco_equalto5 = 0; 1046 ps_cur_slice->u2_frame_num = 0; 1047 1048 ps_dec->i4_max_poc = 0; 1049 ps_dec->i4_prev_max_display_seq = 0; 1050 ps_dec->u1_recon_mb_grp = 4; 1051 1052 /* Field PIC initializations */ 1053 ps_dec->u1_second_field = 0; 1054 ps_dec->s_prev_seq_params.u1_eoseq_pending = 0; 1055 1056 /* Set the cropping parameters as zero */ 1057 ps_dec->u2_crop_offset_y = 0; 1058 ps_dec->u2_crop_offset_uv = 0; 1059 1060 /* The Initial Frame Rate Info is not Present */ 1061 ps_dec->i4_vui_frame_rate = -1; 1062 ps_dec->i4_pic_type = -1; 1063 ps_dec->i4_frametype = -1; 1064 ps_dec->i4_content_type = -1; 1065 1066 ps_dec->u1_res_changed = 0; 1067 1068 1069 ps_dec->u1_frame_decoded_flag = 0; 1070 1071 /* Set the default frame seek mask mode */ 1072 ps_dec->u4_skip_frm_mask = SKIP_NONE; 1073 1074 /********************************************************/ 1075 /* Initialize CAVLC residual decoding function pointers */ 1076 /********************************************************/ 1077 ps_dec->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1; 1078 ps_dec->pf_cavlc_4x4res_block[1] = 1079 ih264d_cavlc_4x4res_block_totalcoeff_2to10; 1080 ps_dec->pf_cavlc_4x4res_block[2] = 1081 ih264d_cavlc_4x4res_block_totalcoeff_11to16; 1082 1083 ps_dec->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7; 1084 ps_dec->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8; 1085 1086 ps_dec->pf_cavlc_parse_8x8block[0] = 1087 ih264d_cavlc_parse_8x8block_none_available; 1088 ps_dec->pf_cavlc_parse_8x8block[1] = 1089 ih264d_cavlc_parse_8x8block_left_available; 1090 ps_dec->pf_cavlc_parse_8x8block[2] = 1091 ih264d_cavlc_parse_8x8block_top_available; 1092 ps_dec->pf_cavlc_parse_8x8block[3] = 1093 ih264d_cavlc_parse_8x8block_both_available; 1094 1095 /***************************************************************************/ 1096 /* Initialize Bs calculation function pointers for P and B, 16x16/non16x16 */ 1097 /***************************************************************************/ 1098 ps_dec->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice; 1099 ps_dec->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice; 1100 1101 ps_dec->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice; 1102 ps_dec->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice; 1103 1104 ps_dec->pf_fill_bs_xtra_left_edge[0] = 1105 ih264d_fill_bs_xtra_left_edge_cur_frm; 1106 ps_dec->pf_fill_bs_xtra_left_edge[1] = 1107 ih264d_fill_bs_xtra_left_edge_cur_fld; 1108 1109 /* Initialize Reference Pic Buffers */ 1110 ih264d_init_ref_bufs(ps_dec->ps_dpb_mgr); 1111 1112 ps_dec->u2_prv_frame_num = 0; 1113 ps_dec->u1_top_bottom_decoded = 0; 1114 ps_dec->u1_dangling_field = 0; 1115 1116 ps_dec->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table; 1117 1118 ps_dec->pu1_left_mv_ctxt_inc = ps_dec->u1_left_mv_ctxt_inc_arr[0]; 1119 ps_dec->pi1_left_ref_idx_ctxt_inc = 1120 &ps_dec->i1_left_ref_idx_ctx_inc_arr[0][0]; 1121 ps_dec->pu1_left_yuv_dc_csbp = &ps_dec->u1_yuv_dc_csbp_topmb; 1122 1123 /* ! */ 1124 /* Initializing flush frame u4_flag */ 1125 ps_dec->u1_flushfrm = 0; 1126 1127 { 1128 ps_dec->s_cab_dec_env.pv_codec_handle = (void*)ps_dec; 1129 ps_dec->ps_bitstrm->pv_codec_handle = (void*)ps_dec; 1130 ps_dec->ps_cur_slice->pv_codec_handle = (void*)ps_dec; 1131 ps_dec->ps_dpb_mgr->pv_codec_handle = (void*)ps_dec; 1132 } 1133 1134 memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t)); 1135 memset(ps_dec->u4_disp_buf_mapping, 0, 1136 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1137 memset(ps_dec->u4_disp_buf_to_be_freed, 0, 1138 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1139 memset(ps_dec->ps_cur_slice, 0, sizeof(dec_slice_params_t)); 1140 1141 ih264d_init_arch(ps_dec); 1142 ih264d_init_function_ptr(ps_dec); 1143 ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT; 1144 ps_dec->init_done = 1; 1145 1146 } 1147 WORD32 ih264d_free_static_bufs(iv_obj_t *dec_hdl) 1148 { 1149 dec_struct_t *ps_dec; 1150 1151 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf); 1152 void *pv_mem_ctxt; 1153 1154 ps_dec = (dec_struct_t *)dec_hdl->pv_codec_handle; 1155 pf_aligned_free = ps_dec->pf_aligned_free; 1156 pv_mem_ctxt = ps_dec->pv_mem_ctxt; 1157 1158 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sps); 1159 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pps); 1160 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_dec_thread_handle); 1161 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_bs_deblk_thread_handle); 1162 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_mgr); 1163 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred); 1164 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_disp_buf_mgr); 1165 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_pic_buf_mgr); 1166 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pic_buf_base); 1167 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_err_status); 1168 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sei); 1169 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_cmds); 1170 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_bitstrm); 1171 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_cur_slice); 1172 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_scratch_sps_pps); 1173 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_static); 1174 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ppv_map_ref_idx_to_poc_base); 1175 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_cabac_ctxt_table_t); 1176 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mb_ctxt_info); 1177 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_ref_buff_base); 1178 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_pred1); 1179 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_temp_mc_buffer); 1180 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_init_dpb_base); 1181 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_mbaff_wt_mat); 1182 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_wts_ofsts_mat); 1183 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mvpred_addr); 1184 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_mv_buf_mgr); 1185 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_col_mv_base); 1186 PS_DEC_ALIGNED_FREE(ps_dec, dec_hdl->pv_codec_handle); 1187 1188 if(dec_hdl) 1189 { 1190 pf_aligned_free(pv_mem_ctxt, dec_hdl); 1191 } 1192 return IV_SUCCESS; 1193 } 1194 /*****************************************************************************/ 1195 /* */ 1196 /* Function Name : ih264d_create */ 1197 /* */ 1198 /* Description : creates decoder */ 1199 /* */ 1200 /* Inputs :iv_obj_t decoder handle */ 1201 /* :pv_api_ip pointer to input structure */ 1202 /* :pv_api_op pointer to output structure */ 1203 /* Outputs : */ 1204 /* Returns : void */ 1205 /* */ 1206 /* Issues : none */ 1207 /* */ 1208 /* Revision History: */ 1209 /* */ 1210 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1211 /* 22 10 2008 100356 Draft */ 1212 /* */ 1213 /*****************************************************************************/ 1214 WORD32 ih264d_allocate_static_bufs(iv_obj_t **dec_hdl, void *pv_api_ip, void *pv_api_op) 1215 { 1216 ih264d_create_ip_t *ps_create_ip; 1217 ih264d_create_op_t *ps_create_op; 1218 void *pv_buf; 1219 UWORD8 *pu1_buf; 1220 dec_struct_t *ps_dec; 1221 void *(*pf_aligned_alloc)(void *pv_mem_ctxt, WORD32 alignment, WORD32 size); 1222 void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf); 1223 void *pv_mem_ctxt; 1224 WORD32 size; 1225 1226 ps_create_ip = (ih264d_create_ip_t *)pv_api_ip; 1227 ps_create_op = (ih264d_create_op_t *)pv_api_op; 1228 1229 ps_create_op->s_ivd_create_op_t.u4_error_code = 0; 1230 1231 pf_aligned_alloc = ps_create_ip->s_ivd_create_ip_t.pf_aligned_alloc; 1232 pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free; 1233 pv_mem_ctxt = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt; 1234 1235 /* Initialize return handle to NULL */ 1236 ps_create_op->s_ivd_create_op_t.pv_handle = NULL; 1237 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(iv_obj_t)); 1238 RETURN_IF((NULL == pv_buf), IV_FAIL); 1239 *dec_hdl = (iv_obj_t *)pv_buf; 1240 ps_create_op->s_ivd_create_op_t.pv_handle = *dec_hdl; 1241 1242 (*dec_hdl)->pv_codec_handle = NULL; 1243 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(dec_struct_t)); 1244 RETURN_IF((NULL == pv_buf), IV_FAIL); 1245 (*dec_hdl)->pv_codec_handle = (dec_struct_t *)pv_buf; 1246 ps_dec = (dec_struct_t *)pv_buf; 1247 1248 memset(ps_dec, 0, sizeof(dec_struct_t)); 1249 1250 #ifndef LOGO_EN 1251 ps_dec->u4_share_disp_buf = ps_create_ip->s_ivd_create_ip_t.u4_share_disp_buf; 1252 #else 1253 ps_dec->u4_share_disp_buf = 0; 1254 #endif 1255 1256 ps_dec->u1_chroma_format = 1257 (UWORD8)(ps_create_ip->s_ivd_create_ip_t.e_output_format); 1258 1259 if((ps_dec->u1_chroma_format != IV_YUV_420P) 1260 && (ps_dec->u1_chroma_format 1261 != IV_YUV_420SP_UV) 1262 && (ps_dec->u1_chroma_format 1263 != IV_YUV_420SP_VU)) 1264 { 1265 ps_dec->u4_share_disp_buf = 0; 1266 } 1267 1268 ps_dec->pf_aligned_alloc = pf_aligned_alloc; 1269 ps_dec->pf_aligned_free = pf_aligned_free; 1270 ps_dec->pv_mem_ctxt = pv_mem_ctxt; 1271 1272 1273 size = ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS); 1274 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1275 RETURN_IF((NULL == pv_buf), IV_FAIL); 1276 ps_dec->ps_sps = pv_buf; 1277 1278 size = (sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS; 1279 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1280 RETURN_IF((NULL == pv_buf), IV_FAIL); 1281 ps_dec->ps_pps = pv_buf; 1282 1283 size = ithread_get_handle_size(); 1284 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1285 RETURN_IF((NULL == pv_buf), IV_FAIL); 1286 ps_dec->pv_dec_thread_handle = pv_buf; 1287 1288 size = ithread_get_handle_size(); 1289 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1290 RETURN_IF((NULL == pv_buf), IV_FAIL); 1291 ps_dec->pv_bs_deblk_thread_handle = pv_buf; 1292 1293 size = sizeof(dpb_manager_t); 1294 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1295 RETURN_IF((NULL == pv_buf), IV_FAIL); 1296 ps_dec->ps_dpb_mgr = pv_buf; 1297 1298 size = sizeof(pred_info_t) * 2 * 32; 1299 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1300 RETURN_IF((NULL == pv_buf), IV_FAIL); 1301 ps_dec->ps_pred = pv_buf; 1302 1303 size = sizeof(disp_mgr_t); 1304 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1305 RETURN_IF((NULL == pv_buf), IV_FAIL); 1306 ps_dec->pv_disp_buf_mgr = pv_buf; 1307 1308 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 1309 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1310 RETURN_IF((NULL == pv_buf), IV_FAIL); 1311 ps_dec->pv_pic_buf_mgr = pv_buf; 1312 1313 size = sizeof(struct pic_buffer_t) * (H264_MAX_REF_PICS * 2); 1314 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1315 RETURN_IF((NULL == pv_buf), IV_FAIL); 1316 ps_dec->ps_pic_buf_base = pv_buf; 1317 1318 size = sizeof(dec_err_status_t); 1319 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1320 RETURN_IF((NULL == pv_buf), IV_FAIL); 1321 ps_dec->ps_dec_err_status = (dec_err_status_t *)pv_buf; 1322 1323 size = sizeof(sei); 1324 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1325 RETURN_IF((NULL == pv_buf), IV_FAIL); 1326 ps_dec->ps_sei = (sei *)pv_buf; 1327 1328 size = sizeof(dpb_commands_t); 1329 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1330 RETURN_IF((NULL == pv_buf), IV_FAIL); 1331 ps_dec->ps_dpb_cmds = (dpb_commands_t *)pv_buf; 1332 1333 size = sizeof(dec_bit_stream_t); 1334 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1335 RETURN_IF((NULL == pv_buf), IV_FAIL); 1336 ps_dec->ps_bitstrm = (dec_bit_stream_t *)pv_buf; 1337 1338 size = sizeof(dec_slice_params_t); 1339 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1340 RETURN_IF((NULL == pv_buf), IV_FAIL); 1341 ps_dec->ps_cur_slice = (dec_slice_params_t *)pv_buf; 1342 1343 size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t)); 1344 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1345 RETURN_IF((NULL == pv_buf), IV_FAIL); 1346 ps_dec->pv_scratch_sps_pps = pv_buf; 1347 1348 1349 ps_dec->u4_static_bits_buf_size = 256000; 1350 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, ps_dec->u4_static_bits_buf_size); 1351 RETURN_IF((NULL == pv_buf), IV_FAIL); 1352 ps_dec->pu1_bits_buf_static = pv_buf; 1353 1354 1355 size = ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC) 1356 * sizeof(void *)); 1357 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1358 RETURN_IF((NULL == pv_buf), IV_FAIL); 1359 ps_dec->ppv_map_ref_idx_to_poc_base = pv_buf; 1360 memset(ps_dec->ppv_map_ref_idx_to_poc_base, 0, size); 1361 1362 ps_dec->ppv_map_ref_idx_to_poc = ps_dec->ppv_map_ref_idx_to_poc_base + OFFSET_MAP_IDX_POC; 1363 1364 1365 size = (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS); 1366 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1367 RETURN_IF((NULL == pv_buf), IV_FAIL); 1368 ps_dec->p_cabac_ctxt_table_t = pv_buf; 1369 1370 1371 1372 size = sizeof(ctxt_inc_mb_info_t); 1373 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1374 RETURN_IF((NULL == pv_buf), IV_FAIL); 1375 ps_dec->ps_left_mb_ctxt_info = pv_buf; 1376 1377 1378 1379 size = MAX_REF_BUF_SIZE * 2; 1380 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1381 RETURN_IF((NULL == pv_buf), IV_FAIL); 1382 ps_dec->pu1_ref_buff_base = pv_buf; 1383 ps_dec->pu1_ref_buff = ps_dec->pu1_ref_buff_base + MAX_REF_BUF_SIZE; 1384 1385 1386 size = ((sizeof(WORD16)) * PRED_BUFFER_WIDTH 1387 * PRED_BUFFER_HEIGHT * 2); 1388 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1389 RETURN_IF((NULL == pv_buf), IV_FAIL); 1390 ps_dec->pi2_pred1 = pv_buf; 1391 1392 1393 size = sizeof(UWORD8) * (MB_LUM_SIZE); 1394 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1395 RETURN_IF((NULL == pv_buf), IV_FAIL); 1396 ps_dec->pu1_temp_mc_buffer = pv_buf; 1397 1398 1399 1400 1401 size = 8 * MAX_REF_BUFS * sizeof(struct pic_buffer_t); 1402 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1403 RETURN_IF((NULL == pv_buf), IV_FAIL); 1404 1405 ps_dec->pu1_init_dpb_base = pv_buf; 1406 pu1_buf = pv_buf; 1407 ps_dec->ps_dpb_mgr->ps_init_dpb[0][0] = (struct pic_buffer_t *)pu1_buf; 1408 1409 pu1_buf += size / 2; 1410 ps_dec->ps_dpb_mgr->ps_init_dpb[1][0] = (struct pic_buffer_t *)pu1_buf; 1411 1412 size = (sizeof(UWORD32) * 3 1413 * (MAX_FRAMES * MAX_FRAMES)) 1414 << 3; 1415 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1416 RETURN_IF((NULL == pv_buf), IV_FAIL); 1417 ps_dec->pu4_mbaff_wt_mat = pv_buf; 1418 1419 size = sizeof(UWORD32) * 2 * 3 1420 * (MAX_FRAMES * MAX_FRAMES); 1421 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1422 RETURN_IF((NULL == pv_buf), IV_FAIL); 1423 ps_dec->pu4_wts_ofsts_mat = pv_buf; 1424 1425 1426 size = (sizeof(neighbouradd_t) << 2); 1427 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1428 RETURN_IF((NULL == pv_buf), IV_FAIL); 1429 ps_dec->ps_left_mvpred_addr = pv_buf; 1430 1431 1432 size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size(); 1433 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1434 RETURN_IF((NULL == pv_buf), IV_FAIL); 1435 ps_dec->pv_mv_buf_mgr = pv_buf; 1436 1437 1438 size = sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2); 1439 pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size); 1440 RETURN_IF((NULL == pv_buf), IV_FAIL); 1441 ps_dec->ps_col_mv_base = pv_buf; 1442 memset(ps_dec->ps_col_mv_base, 0, size); 1443 1444 { 1445 UWORD8 i; 1446 struct pic_buffer_t *ps_init_dpb; 1447 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[0][0]; 1448 for(i = 0; i < 2 * MAX_REF_BUFS; i++) 1449 { 1450 ps_init_dpb->pu1_buf1 = NULL; 1451 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1; 1452 ps_dec->ps_dpb_mgr->ps_init_dpb[0][i] = ps_init_dpb; 1453 ps_dec->ps_dpb_mgr->ps_mod_dpb[0][i] = ps_init_dpb; 1454 ps_init_dpb++; 1455 } 1456 1457 ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[1][0]; 1458 for(i = 0; i < 2 * MAX_REF_BUFS; i++) 1459 { 1460 ps_init_dpb->pu1_buf1 = NULL; 1461 ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1; 1462 ps_dec->ps_dpb_mgr->ps_init_dpb[1][i] = ps_init_dpb; 1463 ps_dec->ps_dpb_mgr->ps_mod_dpb[1][i] = ps_init_dpb; 1464 ps_init_dpb++; 1465 } 1466 } 1467 ih264d_init_decoder(ps_dec); 1468 1469 return IV_SUCCESS; 1470 } 1471 1472 1473 /*****************************************************************************/ 1474 /* */ 1475 /* Function Name : ih264d_create */ 1476 /* */ 1477 /* Description : creates decoder */ 1478 /* */ 1479 /* Inputs :iv_obj_t decoder handle */ 1480 /* :pv_api_ip pointer to input structure */ 1481 /* :pv_api_op pointer to output structure */ 1482 /* Outputs : */ 1483 /* Returns : void */ 1484 /* */ 1485 /* Issues : none */ 1486 /* */ 1487 /* Revision History: */ 1488 /* */ 1489 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1490 /* 22 10 2008 100356 Draft */ 1491 /* */ 1492 /*****************************************************************************/ 1493 WORD32 ih264d_create(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 1494 { 1495 ih264d_create_op_t *ps_create_op; 1496 1497 WORD32 ret; 1498 1499 ps_create_op = (ih264d_create_op_t *)pv_api_op; 1500 1501 ps_create_op->s_ivd_create_op_t.u4_error_code = 0; 1502 1503 ret = ih264d_allocate_static_bufs(&dec_hdl, pv_api_ip, pv_api_op); 1504 1505 /* If allocation of some buffer fails, then free buffers allocated till then */ 1506 if((IV_FAIL == ret) && (NULL != dec_hdl)) 1507 { 1508 ih264d_free_static_bufs(dec_hdl); 1509 ps_create_op->s_ivd_create_op_t.u4_error_code = IVD_MEM_ALLOC_FAILED; 1510 ps_create_op->s_ivd_create_op_t.u4_error_code = 1 << IVD_FATALERROR; 1511 1512 return IV_FAIL; 1513 } 1514 1515 return IV_SUCCESS; 1516 } 1517 1518 /*****************************************************************************/ 1519 /* */ 1520 /* Function Name : ih264d_map_error */ 1521 /* */ 1522 /* Description : Maps error codes to IVD error groups */ 1523 /* */ 1524 /* Inputs : */ 1525 /* Globals : <Does it use any global variables?> */ 1526 /* Outputs : */ 1527 /* Returns : void */ 1528 /* */ 1529 /* Issues : none */ 1530 /* */ 1531 /* Revision History: */ 1532 /* */ 1533 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1534 /* 22 10 2008 100356 Draft */ 1535 /* */ 1536 /*****************************************************************************/ 1537 UWORD32 ih264d_map_error(UWORD32 i4_err_status) 1538 { 1539 UWORD32 temp = 0; 1540 1541 switch(i4_err_status) 1542 { 1543 case ERROR_MEM_ALLOC_ISRAM_T: 1544 case ERROR_MEM_ALLOC_SDRAM_T: 1545 case ERROR_BUF_MGR: 1546 case ERROR_MB_GROUP_ASSGN_T: 1547 case ERROR_FRAME_LIMIT_OVER: 1548 case ERROR_ACTUAL_RESOLUTION_GREATER_THAN_INIT: 1549 case ERROR_PROFILE_NOT_SUPPORTED: 1550 case ERROR_INIT_NOT_DONE: 1551 case IVD_MEM_ALLOC_FAILED: 1552 temp = 1 << IVD_FATALERROR; 1553 H264_DEC_DEBUG_PRINT("\nFatal Error\n"); 1554 break; 1555 1556 case ERROR_DBP_MANAGER_T: 1557 case ERROR_GAPS_IN_FRM_NUM: 1558 case ERROR_UNKNOWN_NAL: 1559 case ERROR_INV_MB_SLC_GRP_T: 1560 case ERROR_MULTIPLE_SLC_GRP_T: 1561 case ERROR_UNKNOWN_LEVEL: 1562 case ERROR_UNAVAIL_PICBUF_T: 1563 case ERROR_UNAVAIL_MVBUF_T: 1564 case ERROR_UNAVAIL_DISPBUF_T: 1565 case ERROR_NUM_REF: 1566 case ERROR_REFIDX_ORDER_T: 1567 case ERROR_PIC0_NOT_FOUND_T: 1568 case ERROR_MB_TYPE: 1569 case ERROR_SUB_MB_TYPE: 1570 case ERROR_CBP: 1571 case ERROR_REF_IDX: 1572 case ERROR_NUM_MV: 1573 case ERROR_CHROMA_PRED_MODE: 1574 case ERROR_INTRAPRED: 1575 case ERROR_NEXT_MB_ADDRESS_T: 1576 case ERROR_MB_ADDRESS_T: 1577 case ERROR_PIC1_NOT_FOUND_T: 1578 case ERROR_CAVLC_NUM_COEFF_T: 1579 case ERROR_CAVLC_SCAN_POS_T: 1580 case ERROR_PRED_WEIGHT_TABLE_T: 1581 case ERROR_CORRUPTED_SLICE: 1582 temp = 1 << IVD_CORRUPTEDDATA; 1583 break; 1584 1585 case ERROR_NOT_SUPP_RESOLUTION: 1586 case ERROR_FEATURE_UNAVAIL: 1587 case ERROR_ACTUAL_LEVEL_GREATER_THAN_INIT: 1588 temp = 1 << IVD_UNSUPPORTEDINPUT; 1589 break; 1590 1591 case ERROR_INVALID_PIC_PARAM: 1592 case ERROR_INVALID_SEQ_PARAM: 1593 case ERROR_EGC_EXCEED_32_1_T: 1594 case ERROR_EGC_EXCEED_32_2_T: 1595 case ERROR_INV_RANGE_TEV_T: 1596 case ERROR_INV_SLC_TYPE_T: 1597 case ERROR_INV_POC_TYPE_T: 1598 case ERROR_INV_RANGE_QP_T: 1599 case ERROR_INV_SPS_PPS_T: 1600 case ERROR_INV_SLICE_HDR_T: 1601 temp = 1 << IVD_CORRUPTEDHEADER; 1602 break; 1603 1604 case ERROR_EOB_FLUSHBITS_T: 1605 case ERROR_EOB_GETBITS_T: 1606 case ERROR_EOB_GETBIT_T: 1607 case ERROR_EOB_BYPASS_T: 1608 case ERROR_EOB_DECISION_T: 1609 case ERROR_EOB_TERMINATE_T: 1610 case ERROR_EOB_READCOEFF4X4CAB_T: 1611 temp = 1 << IVD_INSUFFICIENTDATA; 1612 break; 1613 case ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED: 1614 case ERROR_DISP_WIDTH_RESET_TO_PIC_WIDTH: 1615 temp = 1 << IVD_UNSUPPORTEDPARAM | 1 << IVD_FATALERROR; 1616 break; 1617 1618 case ERROR_DANGLING_FIELD_IN_PIC: 1619 temp = 1 << IVD_APPLIEDCONCEALMENT; 1620 break; 1621 1622 } 1623 1624 return temp; 1625 1626 } 1627 1628 /*****************************************************************************/ 1629 /* */ 1630 /* Function Name : ih264d_video_decode */ 1631 /* */ 1632 /* Description : handle video decode API command */ 1633 /* */ 1634 /* Inputs :iv_obj_t decoder handle */ 1635 /* :pv_api_ip pointer to input structure */ 1636 /* :pv_api_op pointer to output structure */ 1637 /* Outputs : */ 1638 /* Returns : void */ 1639 /* */ 1640 /* Issues : none */ 1641 /* */ 1642 /* Revision History: */ 1643 /* */ 1644 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1645 /* 22 10 2008 100356 Draft */ 1646 /* */ 1647 /*****************************************************************************/ 1648 1649 WORD32 ih264d_video_decode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 1650 { 1651 /* ! */ 1652 1653 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 1654 1655 WORD32 i4_err_status = 0; 1656 UWORD8 *pu1_buf = NULL; 1657 WORD32 buflen; 1658 UWORD32 u4_max_ofst, u4_length_of_start_code = 0; 1659 1660 UWORD32 bytes_consumed = 0; 1661 UWORD32 cur_slice_is_nonref = 0; 1662 UWORD32 u4_next_is_aud; 1663 UWORD32 u4_first_start_code_found = 0; 1664 WORD32 ret = 0,api_ret_value = IV_SUCCESS; 1665 WORD32 header_data_left = 0,frame_data_left = 0; 1666 UWORD8 *pu1_bitstrm_buf; 1667 ivd_video_decode_ip_t *ps_dec_ip; 1668 ivd_video_decode_op_t *ps_dec_op; 1669 1670 ithread_set_name((void*)"Parse_thread"); 1671 1672 ps_dec_ip = (ivd_video_decode_ip_t *)pv_api_ip; 1673 ps_dec_op = (ivd_video_decode_op_t *)pv_api_op; 1674 1675 { 1676 UWORD32 u4_size; 1677 u4_size = ps_dec_op->u4_size; 1678 memset(ps_dec_op, 0, sizeof(ivd_video_decode_op_t)); 1679 ps_dec_op->u4_size = u4_size; 1680 } 1681 1682 ps_dec->pv_dec_out = ps_dec_op; 1683 if(ps_dec->init_done != 1) 1684 { 1685 return IV_FAIL; 1686 } 1687 1688 /*Data memory barries instruction,so that bitstream write by the application is complete*/ 1689 DATA_SYNC(); 1690 1691 if(0 == ps_dec->u1_flushfrm) 1692 { 1693 if(ps_dec_ip->pv_stream_buffer == NULL) 1694 { 1695 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1696 ps_dec_op->u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL; 1697 return IV_FAIL; 1698 } 1699 if(ps_dec_ip->u4_num_Bytes <= 0) 1700 { 1701 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1702 ps_dec_op->u4_error_code |= IVD_DEC_NUMBYTES_INV; 1703 return IV_FAIL; 1704 1705 } 1706 } 1707 ps_dec->u1_pic_decode_done = 0; 1708 1709 ps_dec_op->u4_num_bytes_consumed = 0; 1710 1711 ps_dec->ps_out_buffer = NULL; 1712 1713 if(ps_dec_ip->u4_size 1714 >= offsetof(ivd_video_decode_ip_t, s_out_buffer)) 1715 ps_dec->ps_out_buffer = &ps_dec_ip->s_out_buffer; 1716 1717 ps_dec->u4_fmt_conv_cur_row = 0; 1718 1719 ps_dec->u4_output_present = 0; 1720 ps_dec->s_disp_op.u4_error_code = 1; 1721 ps_dec->u4_fmt_conv_num_rows = FMT_CONV_NUM_ROWS; 1722 if(0 == ps_dec->u4_share_disp_buf 1723 && ps_dec->i4_decode_header == 0) 1724 { 1725 UWORD32 i; 1726 if(ps_dec->ps_out_buffer->u4_num_bufs == 0) 1727 { 1728 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1729 ps_dec_op->u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS; 1730 return IV_FAIL; 1731 } 1732 1733 for(i = 0; i < ps_dec->ps_out_buffer->u4_num_bufs; i++) 1734 { 1735 if(ps_dec->ps_out_buffer->pu1_bufs[i] == NULL) 1736 { 1737 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1738 ps_dec_op->u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL; 1739 return IV_FAIL; 1740 } 1741 1742 if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] == 0) 1743 { 1744 ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM; 1745 ps_dec_op->u4_error_code |= 1746 IVD_DISP_FRM_ZERO_OP_BUF_SIZE; 1747 return IV_FAIL; 1748 } 1749 } 1750 } 1751 1752 if(ps_dec->u4_total_frames_decoded >= NUM_FRAMES_LIMIT) 1753 { 1754 ps_dec_op->u4_error_code = ERROR_FRAME_LIMIT_OVER; 1755 return IV_FAIL; 1756 } 1757 1758 /* ! */ 1759 ps_dec->u4_ts = ps_dec_ip->u4_ts; 1760 1761 ps_dec_op->u4_error_code = 0; 1762 ps_dec_op->e_pic_type = -1; 1763 ps_dec_op->u4_output_present = 0; 1764 ps_dec_op->u4_frame_decoded_flag = 0; 1765 1766 ps_dec->i4_frametype = -1; 1767 ps_dec->i4_content_type = -1; 1768 /* 1769 * For field pictures, set the bottom and top picture decoded u4_flag correctly. 1770 */ 1771 { 1772 if((TOP_FIELD_ONLY | BOT_FIELD_ONLY) == ps_dec->u1_top_bottom_decoded) 1773 { 1774 ps_dec->u1_top_bottom_decoded = 0; 1775 } 1776 } 1777 ps_dec->u4_slice_start_code_found = 0; 1778 1779 /* In case the deocder is not in flush mode(in shared mode), 1780 then decoder has to pick up a buffer to write current frame. 1781 Check if a frame is available in such cases */ 1782 1783 if(ps_dec->u1_init_dec_flag == 1 && ps_dec->u4_share_disp_buf == 1 1784 && ps_dec->u1_flushfrm == 0) 1785 { 1786 UWORD32 i; 1787 1788 WORD32 disp_avail = 0, free_id; 1789 1790 /* Check if at least one buffer is available with the codec */ 1791 /* If not then return to application with error */ 1792 for(i = 0; i < ps_dec->u1_pic_bufs; i++) 1793 { 1794 if(0 == ps_dec->u4_disp_buf_mapping[i] 1795 || 1 == ps_dec->u4_disp_buf_to_be_freed[i]) 1796 { 1797 disp_avail = 1; 1798 break; 1799 } 1800 1801 } 1802 1803 if(0 == disp_avail) 1804 { 1805 /* If something is queued for display wait for that buffer to be returned */ 1806 1807 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL; 1808 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 1809 return (IV_FAIL); 1810 } 1811 1812 while(1) 1813 { 1814 pic_buffer_t *ps_pic_buf; 1815 ps_pic_buf = (pic_buffer_t *)ih264_buf_mgr_get_next_free( 1816 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, &free_id); 1817 1818 if(ps_pic_buf == NULL) 1819 { 1820 UWORD32 i, display_queued = 0; 1821 1822 /* check if any buffer was given for display which is not returned yet */ 1823 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++) 1824 { 1825 if(0 != ps_dec->u4_disp_buf_mapping[i]) 1826 { 1827 display_queued = 1; 1828 break; 1829 } 1830 } 1831 /* If some buffer is queued for display, then codec has to singal an error and wait 1832 for that buffer to be returned. 1833 If nothing is queued for display then codec has ownership of all display buffers 1834 and it can reuse any of the existing buffers and continue decoding */ 1835 1836 if(1 == display_queued) 1837 { 1838 /* If something is queued for display wait for that buffer to be returned */ 1839 ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL; 1840 ps_dec_op->u4_error_code |= (1 1841 << IVD_UNSUPPORTEDPARAM); 1842 return (IV_FAIL); 1843 } 1844 } 1845 else 1846 { 1847 /* If the buffer is with display, then mark it as in use and then look for a buffer again */ 1848 if(1 == ps_dec->u4_disp_buf_mapping[free_id]) 1849 { 1850 ih264_buf_mgr_set_status( 1851 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 1852 free_id, 1853 BUF_MGR_IO); 1854 } 1855 else 1856 { 1857 /** 1858 * Found a free buffer for present call. Release it now. 1859 * Will be again obtained later. 1860 */ 1861 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 1862 free_id, 1863 BUF_MGR_IO); 1864 break; 1865 } 1866 } 1867 } 1868 1869 } 1870 1871 if(ps_dec->u1_flushfrm && ps_dec->u1_init_dec_flag) 1872 { 1873 1874 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer, 1875 &(ps_dec->s_disp_op)); 1876 if(0 == ps_dec->s_disp_op.u4_error_code) 1877 { 1878 ps_dec->u4_fmt_conv_cur_row = 0; 1879 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht; 1880 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op), 1881 ps_dec->u4_fmt_conv_cur_row, 1882 ps_dec->u4_fmt_conv_num_rows); 1883 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows; 1884 ps_dec->u4_output_present = 1; 1885 1886 } 1887 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op)); 1888 1889 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 1890 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 1891 1892 ps_dec_op->u4_new_seq = 0; 1893 1894 ps_dec_op->u4_output_present = ps_dec->u4_output_present; 1895 ps_dec_op->u4_progressive_frame_flag = 1896 ps_dec->s_disp_op.u4_progressive_frame_flag; 1897 ps_dec_op->e_output_format = 1898 ps_dec->s_disp_op.e_output_format; 1899 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf; 1900 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type; 1901 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts; 1902 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id; 1903 1904 /*In the case of flush ,since no frame is decoded set pic type as invalid*/ 1905 ps_dec_op->u4_is_ref_flag = -1; 1906 ps_dec_op->e_pic_type = IV_NA_FRAME; 1907 ps_dec_op->u4_frame_decoded_flag = 0; 1908 1909 if(0 == ps_dec->s_disp_op.u4_error_code) 1910 { 1911 return (IV_SUCCESS); 1912 } 1913 else 1914 return (IV_FAIL); 1915 1916 } 1917 if(ps_dec->u1_res_changed == 1) 1918 { 1919 /*if resolution has changed and all buffers have been flushed, reset decoder*/ 1920 ih264d_init_decoder(ps_dec); 1921 } 1922 1923 ps_dec->u4_prev_nal_skipped = 0; 1924 1925 ps_dec->u2_cur_mb_addr = 0; 1926 ps_dec->u2_total_mbs_coded = 0; 1927 ps_dec->u2_cur_slice_num = 0; 1928 ps_dec->cur_dec_mb_num = 0; 1929 ps_dec->cur_recon_mb_num = 0; 1930 ps_dec->u4_first_slice_in_pic = 2; 1931 ps_dec->u1_first_pb_nal_in_pic = 1; 1932 ps_dec->u1_slice_header_done = 0; 1933 ps_dec->u1_dangling_field = 0; 1934 1935 ps_dec->u4_dec_thread_created = 0; 1936 ps_dec->u4_bs_deblk_thread_created = 0; 1937 ps_dec->u4_cur_bs_mb_num = 0; 1938 ps_dec->u4_start_recon_deblk = 0; 1939 1940 DEBUG_THREADS_PRINTF(" Starting process call\n"); 1941 1942 1943 ps_dec->u4_pic_buf_got = 0; 1944 1945 do 1946 { 1947 WORD32 buf_size; 1948 1949 pu1_buf = (UWORD8*)ps_dec_ip->pv_stream_buffer 1950 + ps_dec_op->u4_num_bytes_consumed; 1951 1952 u4_max_ofst = ps_dec_ip->u4_num_Bytes 1953 - ps_dec_op->u4_num_bytes_consumed; 1954 1955 /* If dynamic bitstream buffer is not allocated and 1956 * header decode is done, then allocate dynamic bitstream buffer 1957 */ 1958 if((NULL == ps_dec->pu1_bits_buf_dynamic) && 1959 (ps_dec->i4_header_decoded & 1)) 1960 { 1961 WORD32 size; 1962 1963 void *pv_buf; 1964 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt; 1965 size = MAX(256000, ps_dec->u2_pic_wd * ps_dec->u2_pic_ht * 3 / 2); 1966 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1967 RETURN_IF((NULL == pv_buf), IV_FAIL); 1968 ps_dec->pu1_bits_buf_dynamic = pv_buf; 1969 ps_dec->u4_dynamic_bits_buf_size = size; 1970 } 1971 1972 if(ps_dec->pu1_bits_buf_dynamic) 1973 { 1974 pu1_bitstrm_buf = ps_dec->pu1_bits_buf_dynamic; 1975 buf_size = ps_dec->u4_dynamic_bits_buf_size; 1976 } 1977 else 1978 { 1979 pu1_bitstrm_buf = ps_dec->pu1_bits_buf_static; 1980 buf_size = ps_dec->u4_static_bits_buf_size; 1981 } 1982 1983 u4_next_is_aud = 0; 1984 1985 buflen = ih264d_find_start_code(pu1_buf, 0, u4_max_ofst, 1986 &u4_length_of_start_code, 1987 &u4_next_is_aud); 1988 1989 if(buflen == -1) 1990 buflen = 0; 1991 /* Ignore bytes beyond the allocated size of intermediate buffer */ 1992 buflen = MIN(buflen, buf_size); 1993 1994 bytes_consumed = buflen + u4_length_of_start_code; 1995 ps_dec_op->u4_num_bytes_consumed += bytes_consumed; 1996 1997 { 1998 UWORD8 u1_firstbyte, u1_nal_ref_idc; 1999 2000 if(ps_dec->i4_app_skip_mode == IVD_SKIP_B) 2001 { 2002 u1_firstbyte = *(pu1_buf + u4_length_of_start_code); 2003 u1_nal_ref_idc = (UWORD8)(NAL_REF_IDC(u1_firstbyte)); 2004 if(u1_nal_ref_idc == 0) 2005 { 2006 /*skip non reference frames*/ 2007 cur_slice_is_nonref = 1; 2008 continue; 2009 } 2010 else 2011 { 2012 if(1 == cur_slice_is_nonref) 2013 { 2014 /*We have encountered a referenced frame,return to app*/ 2015 ps_dec_op->u4_num_bytes_consumed -= 2016 bytes_consumed; 2017 ps_dec_op->e_pic_type = IV_B_FRAME; 2018 ps_dec_op->u4_error_code = 2019 IVD_DEC_FRM_SKIPPED; 2020 ps_dec_op->u4_error_code |= (1 2021 << IVD_UNSUPPORTEDPARAM); 2022 ps_dec_op->u4_frame_decoded_flag = 0; 2023 ps_dec_op->u4_size = 2024 sizeof(ivd_video_decode_op_t); 2025 /*signal the decode thread*/ 2026 ih264d_signal_decode_thread(ps_dec); 2027 /* close deblock thread if it is not closed yet*/ 2028 if(ps_dec->u4_num_cores == 3) 2029 { 2030 ih264d_signal_bs_deblk_thread(ps_dec); 2031 } 2032 2033 return (IV_FAIL); 2034 } 2035 } 2036 2037 } 2038 2039 } 2040 2041 2042 if(buflen) 2043 { 2044 memcpy(pu1_bitstrm_buf, pu1_buf + u4_length_of_start_code, 2045 buflen); 2046 /* Decoder may read extra 8 bytes near end of the frame */ 2047 if((buflen + 8) < buf_size) 2048 { 2049 memset(pu1_bitstrm_buf + buflen, 0, 8); 2050 } 2051 u4_first_start_code_found = 1; 2052 2053 } 2054 else 2055 { 2056 /*start code not found*/ 2057 2058 if(u4_first_start_code_found == 0) 2059 { 2060 /*no start codes found in current process call*/ 2061 2062 ps_dec->i4_error_code = ERROR_START_CODE_NOT_FOUND; 2063 ps_dec_op->u4_error_code |= 1 << IVD_INSUFFICIENTDATA; 2064 2065 if(ps_dec->u4_pic_buf_got == 0) 2066 { 2067 2068 ih264d_fill_output_struct_from_context(ps_dec, 2069 ps_dec_op); 2070 2071 ps_dec_op->u4_error_code = ps_dec->i4_error_code; 2072 ps_dec_op->u4_frame_decoded_flag = 0; 2073 2074 return (IV_FAIL); 2075 } 2076 else 2077 { 2078 ps_dec->u1_pic_decode_done = 1; 2079 continue; 2080 } 2081 } 2082 else 2083 { 2084 /* a start code has already been found earlier in the same process call*/ 2085 frame_data_left = 0; 2086 continue; 2087 } 2088 2089 } 2090 2091 ps_dec->u4_return_to_app = 0; 2092 ret = ih264d_parse_nal_unit(dec_hdl, ps_dec_op, 2093 pu1_bitstrm_buf, buflen); 2094 if(ret != OK) 2095 { 2096 UWORD32 error = ih264d_map_error(ret); 2097 ps_dec_op->u4_error_code = error | ret; 2098 api_ret_value = IV_FAIL; 2099 2100 if((ret == IVD_RES_CHANGED) 2101 || (ret == IVD_MEM_ALLOC_FAILED) 2102 || (ret == ERROR_UNAVAIL_PICBUF_T) 2103 || (ret == ERROR_UNAVAIL_MVBUF_T) 2104 || (ret == ERROR_INV_SPS_PPS_T)) 2105 { 2106 ps_dec->u4_slice_start_code_found = 0; 2107 break; 2108 } 2109 2110 if((ret == ERROR_INCOMPLETE_FRAME) || (ret == ERROR_DANGLING_FIELD_IN_PIC)) 2111 { 2112 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 2113 api_ret_value = IV_FAIL; 2114 break; 2115 } 2116 2117 if(ret == ERROR_IN_LAST_SLICE_OF_PIC) 2118 { 2119 api_ret_value = IV_FAIL; 2120 break; 2121 } 2122 2123 } 2124 2125 if(ps_dec->u4_return_to_app) 2126 { 2127 /*We have encountered a referenced frame,return to app*/ 2128 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 2129 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED; 2130 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 2131 ps_dec_op->u4_frame_decoded_flag = 0; 2132 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t); 2133 /*signal the decode thread*/ 2134 ih264d_signal_decode_thread(ps_dec); 2135 /* close deblock thread if it is not closed yet*/ 2136 if(ps_dec->u4_num_cores == 3) 2137 { 2138 ih264d_signal_bs_deblk_thread(ps_dec); 2139 } 2140 return (IV_FAIL); 2141 2142 } 2143 2144 2145 2146 header_data_left = ((ps_dec->i4_decode_header == 1) 2147 && (ps_dec->i4_header_decoded != 3) 2148 && (ps_dec_op->u4_num_bytes_consumed 2149 < ps_dec_ip->u4_num_Bytes)); 2150 frame_data_left = (((ps_dec->i4_decode_header == 0) 2151 && ((ps_dec->u1_pic_decode_done == 0) 2152 || (u4_next_is_aud == 1))) 2153 && (ps_dec_op->u4_num_bytes_consumed 2154 < ps_dec_ip->u4_num_Bytes)); 2155 } 2156 while(( header_data_left == 1)||(frame_data_left == 1)); 2157 2158 if((ps_dec->u4_slice_start_code_found == 1) 2159 && (ret != IVD_MEM_ALLOC_FAILED) 2160 && ps_dec->u2_total_mbs_coded < ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs) 2161 { 2162 // last slice - missing/corruption 2163 WORD32 num_mb_skipped; 2164 WORD32 prev_slice_err; 2165 pocstruct_t temp_poc; 2166 WORD32 ret1; 2167 2168 num_mb_skipped = (ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs) 2169 - ps_dec->u2_total_mbs_coded; 2170 2171 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_pic_buf_got == 0)) 2172 prev_slice_err = 1; 2173 else 2174 prev_slice_err = 2; 2175 2176 if(ps_dec->u4_first_slice_in_pic && (ps_dec->u2_total_mbs_coded == 0)) 2177 prev_slice_err = 1; 2178 2179 ret1 = ih264d_mark_err_slice_skip(ps_dec, num_mb_skipped, ps_dec->u1_nal_unit_type == IDR_SLICE_NAL, ps_dec->ps_cur_slice->u2_frame_num, 2180 &temp_poc, prev_slice_err); 2181 2182 if((ret1 == ERROR_UNAVAIL_PICBUF_T) || (ret1 == ERROR_UNAVAIL_MVBUF_T)) 2183 { 2184 return IV_FAIL; 2185 } 2186 } 2187 2188 if((ret == IVD_RES_CHANGED) 2189 || (ret == IVD_MEM_ALLOC_FAILED) 2190 || (ret == ERROR_UNAVAIL_PICBUF_T) 2191 || (ret == ERROR_UNAVAIL_MVBUF_T) 2192 || (ret == ERROR_INV_SPS_PPS_T)) 2193 { 2194 2195 /* signal the decode thread */ 2196 ih264d_signal_decode_thread(ps_dec); 2197 /* close deblock thread if it is not closed yet */ 2198 if(ps_dec->u4_num_cores == 3) 2199 { 2200 ih264d_signal_bs_deblk_thread(ps_dec); 2201 } 2202 /* dont consume bitstream for change in resolution case */ 2203 if(ret == IVD_RES_CHANGED) 2204 { 2205 ps_dec_op->u4_num_bytes_consumed -= bytes_consumed; 2206 } 2207 return IV_FAIL; 2208 } 2209 2210 2211 if(ps_dec->u1_separate_parse) 2212 { 2213 /* If Format conversion is not complete, 2214 complete it here */ 2215 if(ps_dec->u4_num_cores == 2) 2216 { 2217 2218 /*do deblocking of all mbs*/ 2219 if((ps_dec->u4_nmb_deblk == 0) &&(ps_dec->u4_start_recon_deblk == 1) && (ps_dec->ps_cur_sps->u1_mb_aff_flag == 0)) 2220 { 2221 UWORD32 u4_num_mbs,u4_max_addr; 2222 tfr_ctxt_t s_tfr_ctxt; 2223 tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt; 2224 pad_mgr_t *ps_pad_mgr = &ps_dec->s_pad_mgr; 2225 2226 /*BS is done for all mbs while parsing*/ 2227 u4_max_addr = (ps_dec->u2_frm_wd_in_mbs * ps_dec->u2_frm_ht_in_mbs) - 1; 2228 ps_dec->u4_cur_bs_mb_num = u4_max_addr + 1; 2229 2230 2231 ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt, 2232 ps_dec->u2_frm_wd_in_mbs, 0); 2233 2234 2235 u4_num_mbs = u4_max_addr 2236 - ps_dec->u4_cur_deblk_mb_num + 1; 2237 2238 DEBUG_PERF_PRINTF("mbs left for deblocking= %d \n",u4_num_mbs); 2239 2240 if(u4_num_mbs != 0) 2241 ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs, 2242 ps_tfr_cxt,1); 2243 2244 ps_dec->u4_start_recon_deblk = 0; 2245 2246 } 2247 2248 } 2249 2250 /*signal the decode thread*/ 2251 ih264d_signal_decode_thread(ps_dec); 2252 /* close deblock thread if it is not closed yet*/ 2253 if(ps_dec->u4_num_cores == 3) 2254 { 2255 ih264d_signal_bs_deblk_thread(ps_dec); 2256 } 2257 } 2258 2259 2260 DATA_SYNC(); 2261 2262 2263 if((ps_dec_op->u4_error_code & 0xff) 2264 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED) 2265 { 2266 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 2267 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 2268 } 2269 2270 //Report if header (sps and pps) has not been decoded yet 2271 if(ps_dec->i4_header_decoded != 3) 2272 { 2273 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA); 2274 2275 } 2276 2277 if(ps_dec->i4_decode_header == 1 && ps_dec->i4_header_decoded != 3) 2278 { 2279 ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA); 2280 2281 } 2282 if(ps_dec->u4_prev_nal_skipped) 2283 { 2284 /*We have encountered a referenced frame,return to app*/ 2285 ps_dec_op->u4_error_code = IVD_DEC_FRM_SKIPPED; 2286 ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 2287 ps_dec_op->u4_frame_decoded_flag = 0; 2288 ps_dec_op->u4_size = sizeof(ivd_video_decode_op_t); 2289 /* close deblock thread if it is not closed yet*/ 2290 if(ps_dec->u4_num_cores == 3) 2291 { 2292 ih264d_signal_bs_deblk_thread(ps_dec); 2293 } 2294 return (IV_FAIL); 2295 2296 } 2297 2298 if((ps_dec->u4_slice_start_code_found == 1) 2299 && (ERROR_DANGLING_FIELD_IN_PIC != i4_err_status)) 2300 { 2301 /* 2302 * For field pictures, set the bottom and top picture decoded u4_flag correctly. 2303 */ 2304 2305 if(ps_dec->ps_cur_slice->u1_field_pic_flag) 2306 { 2307 if(1 == ps_dec->ps_cur_slice->u1_bottom_field_flag) 2308 { 2309 ps_dec->u1_top_bottom_decoded |= BOT_FIELD_ONLY; 2310 } 2311 else 2312 { 2313 ps_dec->u1_top_bottom_decoded |= TOP_FIELD_ONLY; 2314 } 2315 } 2316 2317 /* if new frame in not found (if we are still getting slices from previous frame) 2318 * ih264d_deblock_display is not called. Such frames will not be added to reference /display 2319 */ 2320 if((ps_dec->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0) 2321 { 2322 /* Calling Function to deblock Picture and Display */ 2323 ret = ih264d_deblock_display(ps_dec); 2324 if(ret != 0) 2325 { 2326 return IV_FAIL; 2327 } 2328 } 2329 2330 2331 /*set to complete ,as we dont support partial frame decode*/ 2332 if(ps_dec->i4_header_decoded == 3) 2333 { 2334 ps_dec->u2_total_mbs_coded = ps_dec->ps_cur_sps->u2_max_mb_addr + 1; 2335 } 2336 2337 /*Update the i4_frametype at the end of picture*/ 2338 if(ps_dec->ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL) 2339 { 2340 ps_dec->i4_frametype = IV_IDR_FRAME; 2341 } 2342 else if(ps_dec->i4_pic_type == B_SLICE) 2343 { 2344 ps_dec->i4_frametype = IV_B_FRAME; 2345 } 2346 else if(ps_dec->i4_pic_type == P_SLICE) 2347 { 2348 ps_dec->i4_frametype = IV_P_FRAME; 2349 } 2350 else if(ps_dec->i4_pic_type == I_SLICE) 2351 { 2352 ps_dec->i4_frametype = IV_I_FRAME; 2353 } 2354 else 2355 { 2356 H264_DEC_DEBUG_PRINT("Shouldn't come here\n"); 2357 } 2358 2359 //Update the content type 2360 ps_dec->i4_content_type = ps_dec->ps_cur_slice->u1_field_pic_flag; 2361 2362 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded + 2; 2363 ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded 2364 - ps_dec->ps_cur_slice->u1_field_pic_flag; 2365 2366 } 2367 2368 /* close deblock thread if it is not closed yet*/ 2369 if(ps_dec->u4_num_cores == 3) 2370 { 2371 ih264d_signal_bs_deblk_thread(ps_dec); 2372 } 2373 2374 2375 { 2376 /* In case the decoder is configured to run in low delay mode, 2377 * then get display buffer and then format convert. 2378 * Note in this mode, format conversion does not run paralelly in a thread and adds to the codec cycles 2379 */ 2380 2381 if((IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode) 2382 && ps_dec->u1_init_dec_flag) 2383 { 2384 2385 ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer, 2386 &(ps_dec->s_disp_op)); 2387 if(0 == ps_dec->s_disp_op.u4_error_code) 2388 { 2389 ps_dec->u4_fmt_conv_cur_row = 0; 2390 ps_dec->u4_output_present = 1; 2391 } 2392 } 2393 2394 ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op); 2395 2396 /* If Format conversion is not complete, 2397 complete it here */ 2398 if(ps_dec->u4_output_present && 2399 (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht)) 2400 { 2401 ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht 2402 - ps_dec->u4_fmt_conv_cur_row; 2403 ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op), 2404 ps_dec->u4_fmt_conv_cur_row, 2405 ps_dec->u4_fmt_conv_num_rows); 2406 ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows; 2407 } 2408 2409 ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op)); 2410 } 2411 2412 if(ps_dec->i4_decode_header == 1 && (ps_dec->i4_header_decoded & 1) == 1) 2413 { 2414 ps_dec_op->u4_progressive_frame_flag = 1; 2415 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 2416 { 2417 if((0 == ps_dec->ps_sps->u1_frame_mbs_only_flag) 2418 && (0 == ps_dec->ps_sps->u1_mb_aff_flag)) 2419 ps_dec_op->u4_progressive_frame_flag = 0; 2420 2421 } 2422 } 2423 2424 /*Data memory barrier instruction,so that yuv write by the library is complete*/ 2425 DATA_SYNC(); 2426 2427 H264_DEC_DEBUG_PRINT("The num bytes consumed: %d\n", 2428 ps_dec_op->u4_num_bytes_consumed); 2429 return api_ret_value; 2430 } 2431 2432 WORD32 ih264d_get_version(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2433 { 2434 char version_string[MAXVERSION_STRLEN + 1]; 2435 UWORD32 version_string_len; 2436 2437 ivd_ctl_getversioninfo_ip_t *ps_ip; 2438 ivd_ctl_getversioninfo_op_t *ps_op; 2439 2440 ps_ip = (ivd_ctl_getversioninfo_ip_t *)pv_api_ip; 2441 ps_op = (ivd_ctl_getversioninfo_op_t *)pv_api_op; 2442 UNUSED(dec_hdl); 2443 ps_op->u4_error_code = IV_SUCCESS; 2444 2445 VERSION(version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER, 2446 CODEC_VENDOR); 2447 2448 if((WORD32)ps_ip->u4_version_buffer_size <= 0) 2449 { 2450 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT; 2451 return (IV_FAIL); 2452 } 2453 2454 version_string_len = strnlen(version_string, MAXVERSION_STRLEN) + 1; 2455 2456 if(ps_ip->u4_version_buffer_size >= version_string_len) //(WORD32)sizeof(sizeof(version_string))) 2457 { 2458 memcpy(ps_ip->pv_version_buffer, version_string, version_string_len); 2459 ps_op->u4_error_code = IV_SUCCESS; 2460 } 2461 else 2462 { 2463 ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT; 2464 return IV_FAIL; 2465 } 2466 return (IV_SUCCESS); 2467 } 2468 2469 /*****************************************************************************/ 2470 /* */ 2471 /* Function Name : ih264d_get_display_frame */ 2472 /* */ 2473 /* Description : */ 2474 /* Inputs :iv_obj_t decoder handle */ 2475 /* :pv_api_ip pointer to input structure */ 2476 /* :pv_api_op pointer to output structure */ 2477 /* Outputs : */ 2478 /* Returns : void */ 2479 /* */ 2480 /* Issues : none */ 2481 /* */ 2482 /* Revision History: */ 2483 /* */ 2484 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2485 /* 22 10 2008 100356 Draft */ 2486 /* */ 2487 /*****************************************************************************/ 2488 WORD32 ih264d_get_display_frame(iv_obj_t *dec_hdl, 2489 void *pv_api_ip, 2490 void *pv_api_op) 2491 { 2492 2493 UNUSED(dec_hdl); 2494 UNUSED(pv_api_ip); 2495 UNUSED(pv_api_op); 2496 // This function is no longer needed, output is returned in the process() 2497 return IV_FAIL; 2498 } 2499 2500 /*****************************************************************************/ 2501 /* */ 2502 /* Function Name : ih264d_set_display_frame */ 2503 /* */ 2504 /* Description : */ 2505 /* */ 2506 /* Inputs :iv_obj_t decoder handle */ 2507 /* :pv_api_ip pointer to input structure */ 2508 /* :pv_api_op pointer to output structure */ 2509 /* Outputs : */ 2510 /* Returns : void */ 2511 /* */ 2512 /* Issues : none */ 2513 /* */ 2514 /* Revision History: */ 2515 /* */ 2516 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2517 /* 22 10 2008 100356 Draft */ 2518 /* */ 2519 /*****************************************************************************/ 2520 WORD32 ih264d_set_display_frame(iv_obj_t *dec_hdl, 2521 void *pv_api_ip, 2522 void *pv_api_op) 2523 { 2524 2525 ivd_set_display_frame_ip_t *dec_disp_ip; 2526 ivd_set_display_frame_op_t *dec_disp_op; 2527 2528 UWORD32 i; 2529 dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2530 2531 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip; 2532 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op; 2533 dec_disp_op->u4_error_code = 0; 2534 2535 2536 ps_dec->u4_num_disp_bufs = 0; 2537 if(ps_dec->u4_share_disp_buf) 2538 { 2539 UWORD32 u4_num_bufs = dec_disp_ip->num_disp_bufs; 2540 2541 u4_num_bufs = MIN(u4_num_bufs, MAX_DISP_BUFS_NEW); 2542 2543 ps_dec->u4_num_disp_bufs = u4_num_bufs; 2544 for(i = 0; i < u4_num_bufs; i++) 2545 { 2546 ps_dec->disp_bufs[i].u4_num_bufs = 2547 dec_disp_ip->s_disp_buffer[i].u4_num_bufs; 2548 2549 ps_dec->disp_bufs[i].buf[0] = 2550 dec_disp_ip->s_disp_buffer[i].pu1_bufs[0]; 2551 ps_dec->disp_bufs[i].buf[1] = 2552 dec_disp_ip->s_disp_buffer[i].pu1_bufs[1]; 2553 ps_dec->disp_bufs[i].buf[2] = 2554 dec_disp_ip->s_disp_buffer[i].pu1_bufs[2]; 2555 2556 ps_dec->disp_bufs[i].u4_bufsize[0] = 2557 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]; 2558 ps_dec->disp_bufs[i].u4_bufsize[1] = 2559 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]; 2560 ps_dec->disp_bufs[i].u4_bufsize[2] = 2561 dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]; 2562 2563 } 2564 } 2565 return IV_SUCCESS; 2566 2567 } 2568 2569 /*****************************************************************************/ 2570 /* */ 2571 /* Function Name : ih264d_set_flush_mode */ 2572 /* */ 2573 /* Description : */ 2574 /* */ 2575 /* Inputs :iv_obj_t decoder handle */ 2576 /* :pv_api_ip pointer to input structure */ 2577 /* :pv_api_op pointer to output structure */ 2578 /* Globals : <Does it use any global variables?> */ 2579 /* Outputs : */ 2580 /* Returns : void */ 2581 /* */ 2582 /* Issues : none */ 2583 /* */ 2584 /* Revision History: */ 2585 /* */ 2586 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2587 /* 22 10 2008 100356 Draft */ 2588 /* */ 2589 /*****************************************************************************/ 2590 WORD32 ih264d_set_flush_mode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2591 { 2592 dec_struct_t * ps_dec; 2593 ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op; 2594 ps_ctl_op->u4_error_code = 0; 2595 2596 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2597 UNUSED(pv_api_ip); 2598 /* ! */ 2599 /* Signal flush frame control call */ 2600 ps_dec->u1_flushfrm = 1; 2601 2602 if(ps_dec->u1_init_dec_flag == 1) 2603 { 2604 ih264d_release_pics_in_dpb((void *)ps_dec, ps_dec->u1_pic_bufs); 2605 ih264d_release_display_bufs(ps_dec); 2606 } 2607 2608 ps_ctl_op->u4_error_code = 0; 2609 2610 return IV_SUCCESS; 2611 } 2612 2613 /*****************************************************************************/ 2614 /* */ 2615 /* Function Name : ih264d_get_status */ 2616 /* */ 2617 /* Description : */ 2618 /* */ 2619 /* Inputs :iv_obj_t decoder handle */ 2620 /* :pv_api_ip pointer to input structure */ 2621 /* :pv_api_op pointer to output structure */ 2622 /* Globals : <Does it use any global variables?> */ 2623 /* Outputs : */ 2624 /* Returns : void */ 2625 /* */ 2626 /* Issues : none */ 2627 /* */ 2628 /* Revision History: */ 2629 /* */ 2630 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2631 /* 22 10 2008 100356 Draft */ 2632 /* */ 2633 /*****************************************************************************/ 2634 2635 WORD32 ih264d_get_status(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2636 { 2637 2638 UWORD32 i; 2639 dec_struct_t * ps_dec; 2640 UWORD32 pic_wd, pic_ht; 2641 ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op; 2642 UNUSED(pv_api_ip); 2643 ps_ctl_op->u4_error_code = 0; 2644 2645 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2646 2647 2648 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 2649 { 2650 ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height; 2651 ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width; 2652 2653 if(0 == ps_dec->u4_share_disp_buf) 2654 { 2655 pic_wd = ps_dec->u2_disp_width; 2656 pic_ht = ps_dec->u2_disp_height; 2657 2658 } 2659 else 2660 { 2661 pic_wd = ps_dec->u2_frm_wd_y; 2662 pic_ht = ps_dec->u2_frm_ht_y; 2663 } 2664 } 2665 else 2666 { 2667 pic_wd = 0; 2668 pic_ht = 0; 2669 2670 ps_ctl_op->u4_pic_ht = pic_wd; 2671 ps_ctl_op->u4_pic_wd = pic_ht; 2672 2673 if(1 == ps_dec->u4_share_disp_buf) 2674 { 2675 pic_wd += (PAD_LEN_Y_H << 1); 2676 pic_ht += (PAD_LEN_Y_V << 2); 2677 2678 } 2679 2680 } 2681 2682 if(ps_dec->u4_app_disp_width > pic_wd) 2683 pic_wd = ps_dec->u4_app_disp_width; 2684 if(0 == ps_dec->u4_share_disp_buf) 2685 ps_ctl_op->u4_num_disp_bufs = 1; 2686 else 2687 { 2688 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 2689 { 2690 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) && 2691 (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag)) 2692 { 2693 ps_ctl_op->u4_num_disp_bufs = 2694 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1; 2695 } 2696 else 2697 { 2698 /*if VUI is not present assume maximum possible refrence frames for the level, 2699 * as max reorder frames*/ 2700 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps); 2701 } 2702 2703 ps_ctl_op->u4_num_disp_bufs += 2704 ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 2705 } 2706 else 2707 { 2708 ps_ctl_op->u4_num_disp_bufs = 32; 2709 } 2710 ps_ctl_op->u4_num_disp_bufs = MAX( 2711 ps_ctl_op->u4_num_disp_bufs, 6); 2712 ps_ctl_op->u4_num_disp_bufs = MIN( 2713 ps_ctl_op->u4_num_disp_bufs, 32); 2714 } 2715 2716 ps_ctl_op->u4_error_code = ps_dec->i4_error_code; 2717 2718 ps_ctl_op->u4_frame_rate = 0; //make it proper 2719 ps_ctl_op->u4_bit_rate = 0; //make it proper 2720 ps_ctl_op->e_content_type = ps_dec->i4_content_type; 2721 ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format; 2722 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS; 2723 2724 if(ps_dec->u1_chroma_format == IV_YUV_420P) 2725 { 2726 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420; 2727 } 2728 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 2729 { 2730 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE; 2731 } 2732 else if(ps_dec->u1_chroma_format == IV_RGB_565) 2733 { 2734 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565; 2735 } 2736 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2737 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 2738 { 2739 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP; 2740 } 2741 2742 else 2743 { 2744 //Invalid chroma format; Error code may be updated, verify in testing if needed 2745 ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL; 2746 return IV_FAIL; 2747 } 2748 2749 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++) 2750 { 2751 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2); 2752 } 2753 2754 /*!*/ 2755 if(ps_dec->u1_chroma_format == IV_YUV_420P) 2756 { 2757 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 2758 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 2759 >> 2; 2760 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht) 2761 >> 2; 2762 } 2763 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 2764 { 2765 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 2766 * 2; 2767 ps_ctl_op->u4_min_out_buf_size[1] = 2768 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2769 } 2770 else if(ps_dec->u1_chroma_format == IV_RGB_565) 2771 { 2772 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 2773 * 2; 2774 ps_ctl_op->u4_min_out_buf_size[1] = 2775 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2776 } 2777 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2778 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 2779 { 2780 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 2781 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 2782 >> 1; 2783 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2784 } 2785 2786 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs; 2787 return IV_SUCCESS; 2788 } 2789 2790 /*****************************************************************************/ 2791 /* */ 2792 /* Function Name : ih264d_get_buf_info */ 2793 /* */ 2794 /* Description : */ 2795 /* */ 2796 /* Inputs :iv_obj_t decoder handle */ 2797 /* :pv_api_ip pointer to input structure */ 2798 /* :pv_api_op pointer to output structure */ 2799 /* Globals : <Does it use any global variables?> */ 2800 /* Outputs : */ 2801 /* Returns : void */ 2802 /* */ 2803 /* Issues : none */ 2804 /* */ 2805 /* Revision History: */ 2806 /* */ 2807 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2808 /* 22 10 2008 100356 Draft */ 2809 /* */ 2810 /*****************************************************************************/ 2811 WORD32 ih264d_get_buf_info(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2812 { 2813 2814 dec_struct_t * ps_dec; 2815 UWORD8 i = 0; // Default for 420P format 2816 UWORD16 pic_wd, pic_ht; 2817 ivd_ctl_getbufinfo_op_t *ps_ctl_op = 2818 (ivd_ctl_getbufinfo_op_t*)pv_api_op; 2819 UNUSED(pv_api_ip); 2820 ps_ctl_op->u4_error_code = 0; 2821 2822 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2823 2824 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS; 2825 if(ps_dec->u1_chroma_format == IV_YUV_420P) 2826 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420; 2827 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 2828 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE; 2829 else if(ps_dec->u1_chroma_format == IV_RGB_565) 2830 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565; 2831 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2832 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 2833 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP; 2834 2835 else 2836 { 2837 //Invalid chroma format; Error code may be updated, verify in testing if needed 2838 return IV_FAIL; 2839 } 2840 2841 ps_ctl_op->u4_num_disp_bufs = 1; 2842 2843 2844 pic_wd = 0; 2845 pic_ht = 0; 2846 2847 if(ps_dec->i4_header_decoded == 3) 2848 { 2849 2850 if(0 == ps_dec->u4_share_disp_buf) 2851 { 2852 pic_wd = ps_dec->u2_disp_width; 2853 pic_ht = ps_dec->u2_disp_height; 2854 2855 } 2856 else 2857 { 2858 pic_wd = ps_dec->u2_frm_wd_y; 2859 pic_ht = ps_dec->u2_frm_ht_y; 2860 } 2861 2862 } 2863 2864 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++) 2865 { 2866 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2); 2867 } 2868 if((WORD32)ps_dec->u4_app_disp_width > pic_wd) 2869 pic_wd = ps_dec->u4_app_disp_width; 2870 2871 if(0 == ps_dec->u4_share_disp_buf) 2872 ps_ctl_op->u4_num_disp_bufs = 1; 2873 else 2874 { 2875 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 2876 { 2877 if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) && 2878 (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag)) 2879 { 2880 ps_ctl_op->u4_num_disp_bufs = 2881 ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1; 2882 } 2883 else 2884 { 2885 /*if VUI is not present assume maximum possible refrence frames for the level, 2886 * as max reorder frames*/ 2887 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps); 2888 } 2889 2890 ps_ctl_op->u4_num_disp_bufs += 2891 ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 2892 2893 } 2894 else 2895 { 2896 ps_ctl_op->u4_num_disp_bufs = 32; 2897 2898 } 2899 2900 ps_ctl_op->u4_num_disp_bufs = MAX( 2901 ps_ctl_op->u4_num_disp_bufs, 6); 2902 ps_ctl_op->u4_num_disp_bufs = MIN( 2903 ps_ctl_op->u4_num_disp_bufs, 32); 2904 } 2905 2906 /*!*/ 2907 if(ps_dec->u1_chroma_format == IV_YUV_420P) 2908 { 2909 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 2910 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 2911 >> 2; 2912 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht) 2913 >> 2; 2914 } 2915 else if(ps_dec->u1_chroma_format == IV_YUV_422ILE) 2916 { 2917 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 2918 * 2; 2919 ps_ctl_op->u4_min_out_buf_size[1] = 2920 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2921 } 2922 else if(ps_dec->u1_chroma_format == IV_RGB_565) 2923 { 2924 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht) 2925 * 2; 2926 ps_ctl_op->u4_min_out_buf_size[1] = 2927 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2928 } 2929 else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2930 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 2931 { 2932 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht); 2933 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht) 2934 >> 1; 2935 ps_ctl_op->u4_min_out_buf_size[2] = 0; 2936 } 2937 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs; 2938 2939 return IV_SUCCESS; 2940 } 2941 2942 /*****************************************************************************/ 2943 /* */ 2944 /* Function Name : ih264d_set_params */ 2945 /* */ 2946 /* Description : */ 2947 /* */ 2948 /* Inputs :iv_obj_t decoder handle */ 2949 /* :pv_api_ip pointer to input structure */ 2950 /* :pv_api_op pointer to output structure */ 2951 /* Outputs : */ 2952 /* Returns : void */ 2953 /* */ 2954 /* Issues : none */ 2955 /* */ 2956 /* Revision History: */ 2957 /* */ 2958 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 2959 /* 22 10 2008 100356 Draft */ 2960 /* */ 2961 /*****************************************************************************/ 2962 WORD32 ih264d_set_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 2963 { 2964 2965 dec_struct_t * ps_dec; 2966 WORD32 ret = IV_SUCCESS; 2967 2968 ivd_ctl_set_config_ip_t *ps_ctl_ip = 2969 (ivd_ctl_set_config_ip_t *)pv_api_ip; 2970 ivd_ctl_set_config_op_t *ps_ctl_op = 2971 (ivd_ctl_set_config_op_t *)pv_api_op; 2972 2973 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 2974 2975 ps_dec->u4_skip_frm_mask = 0; 2976 2977 ps_ctl_op->u4_error_code = 0; 2978 2979 ps_dec->i4_app_skip_mode = ps_ctl_ip->e_frm_skip_mode; 2980 2981 /*Is it really supported test it when you so the corner testing using test app*/ 2982 2983 if(ps_ctl_ip->e_frm_skip_mode != IVD_SKIP_NONE) 2984 { 2985 2986 if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_P) 2987 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT; 2988 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_B) 2989 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT; 2990 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_PB) 2991 { 2992 ps_dec->u4_skip_frm_mask |= 1 << B_SLC_BIT; 2993 ps_dec->u4_skip_frm_mask |= 1 << P_SLC_BIT; 2994 } 2995 else if(ps_ctl_ip->e_frm_skip_mode == IVD_SKIP_I) 2996 ps_dec->u4_skip_frm_mask |= 1 << I_SLC_BIT; 2997 else 2998 { 2999 //dynamic parameter not supported 3000 //Put an appropriate error code to return the error.. 3001 //when you do the error code tests and after that remove this comment 3002 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 3003 ret = IV_FAIL; 3004 } 3005 } 3006 3007 if((0 != ps_dec->u4_app_disp_width) 3008 && (ps_ctl_ip->u4_disp_wd 3009 != ps_dec->u4_app_disp_width)) 3010 { 3011 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 3012 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID; 3013 ret = IV_FAIL; 3014 } 3015 else 3016 { 3017 if(ps_ctl_ip->u4_disp_wd >= ps_dec->u2_pic_wd) 3018 { 3019 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd; 3020 } 3021 else if(0 == ps_dec->i4_header_decoded) 3022 { 3023 ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd; 3024 } 3025 else if(ps_ctl_ip->u4_disp_wd == 0) 3026 { 3027 ps_dec->u4_app_disp_width = 0; 3028 } 3029 else 3030 { 3031 /* 3032 * Set the display width to zero. This will ensure that the wrong value we had stored (0xFFFFFFFF) 3033 * does not propogate. 3034 */ 3035 ps_dec->u4_app_disp_width = 0; 3036 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM); 3037 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID; 3038 ret = IV_FAIL; 3039 } 3040 } 3041 if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_FRAME) 3042 ps_dec->i4_decode_header = 0; 3043 else if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_HEADER) 3044 ps_dec->i4_decode_header = 1; 3045 else 3046 { 3047 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 3048 ps_dec->i4_decode_header = 1; 3049 ret = IV_FAIL; 3050 } 3051 ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT; 3052 3053 if((ps_ctl_ip->e_frm_out_mode != IVD_DECODE_FRAME_OUT) && 3054 (ps_ctl_ip->e_frm_out_mode != IVD_DISPLAY_FRAME_OUT)) 3055 { 3056 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM); 3057 ret = IV_FAIL; 3058 } 3059 ps_dec->e_frm_out_mode = ps_ctl_ip->e_frm_out_mode; 3060 return ret; 3061 3062 } 3063 3064 /*****************************************************************************/ 3065 /* */ 3066 /* Function Name : ih264d_set_default_params */ 3067 /* */ 3068 /* Description : */ 3069 /* */ 3070 /* Inputs :iv_obj_t decoder handle */ 3071 /* :pv_api_ip pointer to input structure */ 3072 /* :pv_api_op pointer to output structure */ 3073 /* Outputs : */ 3074 /* Returns : void */ 3075 /* */ 3076 /* Issues : none */ 3077 /* */ 3078 /* Revision History: */ 3079 /* */ 3080 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3081 /* 08 08 2011 100421 Copied from set_params */ 3082 /* */ 3083 /*****************************************************************************/ 3084 WORD32 ih264d_set_default_params(iv_obj_t *dec_hdl, 3085 void *pv_api_ip, 3086 void *pv_api_op) 3087 { 3088 3089 dec_struct_t * ps_dec; 3090 WORD32 ret = IV_SUCCESS; 3091 3092 ivd_ctl_set_config_op_t *ps_ctl_op = 3093 (ivd_ctl_set_config_op_t *)pv_api_op; 3094 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3095 UNUSED(pv_api_ip); 3096 3097 3098 { 3099 ps_dec->u4_app_disp_width = 0; 3100 ps_dec->u4_skip_frm_mask = 0; 3101 ps_dec->i4_decode_header = 1; 3102 3103 ps_ctl_op->u4_error_code = 0; 3104 } 3105 3106 3107 return ret; 3108 } 3109 /*****************************************************************************/ 3110 /* */ 3111 /* Function Name : ih264d_reset */ 3112 /* */ 3113 /* Description : */ 3114 /* */ 3115 /* Inputs :iv_obj_t decoder handle */ 3116 /* :pv_api_ip pointer to input structure */ 3117 /* :pv_api_op pointer to output structure */ 3118 /* Globals : <Does it use any global variables?> */ 3119 /* Outputs : */ 3120 /* Returns : void */ 3121 /* */ 3122 /* Issues : none */ 3123 /* */ 3124 /* Revision History: */ 3125 /* */ 3126 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3127 /* 22 10 2008 100356 Draft */ 3128 /* */ 3129 /*****************************************************************************/ 3130 WORD32 ih264d_delete(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3131 { 3132 dec_struct_t *ps_dec; 3133 ih264d_delete_ip_t *ps_ip = (ih264d_delete_ip_t *)pv_api_ip; 3134 ih264d_delete_op_t *ps_op = (ih264d_delete_op_t *)pv_api_op; 3135 3136 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3137 UNUSED(ps_ip); 3138 ps_op->s_ivd_delete_op_t.u4_error_code = 0; 3139 ih264d_free_dynamic_bufs(ps_dec); 3140 ih264d_free_static_bufs(dec_hdl); 3141 return IV_SUCCESS; 3142 } 3143 /*****************************************************************************/ 3144 /* */ 3145 /* Function Name : ih264d_reset */ 3146 /* */ 3147 /* Description : */ 3148 /* */ 3149 /* Inputs :iv_obj_t decoder handle */ 3150 /* :pv_api_ip pointer to input structure */ 3151 /* :pv_api_op pointer to output structure */ 3152 /* Globals : <Does it use any global variables?> */ 3153 /* Outputs : */ 3154 /* Returns : void */ 3155 /* */ 3156 /* Issues : none */ 3157 /* */ 3158 /* Revision History: */ 3159 /* */ 3160 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3161 /* 22 10 2008 100356 Draft */ 3162 /* */ 3163 /*****************************************************************************/ 3164 WORD32 ih264d_reset(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3165 { 3166 dec_struct_t * ps_dec; 3167 ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op; 3168 UNUSED(pv_api_ip); 3169 ps_ctl_op->u4_error_code = 0; 3170 3171 ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle); 3172 3173 if(ps_dec != NULL) 3174 { 3175 ih264d_init_decoder(ps_dec); 3176 } 3177 else 3178 { 3179 H264_DEC_DEBUG_PRINT( 3180 "\nReset called without Initializing the decoder\n"); 3181 ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE; 3182 } 3183 3184 return IV_SUCCESS; 3185 } 3186 3187 /*****************************************************************************/ 3188 /* */ 3189 /* Function Name : ih264d_ctl */ 3190 /* */ 3191 /* Description : */ 3192 /* */ 3193 /* Inputs :iv_obj_t decoder handle */ 3194 /* :pv_api_ip pointer to input structure */ 3195 /* :pv_api_op pointer to output structure */ 3196 /* Outputs : */ 3197 /* Returns : void */ 3198 /* */ 3199 /* Issues : none */ 3200 /* */ 3201 /* Revision History: */ 3202 /* */ 3203 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3204 /* 22 10 2008 100356 Draft */ 3205 /* */ 3206 /*****************************************************************************/ 3207 WORD32 ih264d_ctl(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3208 { 3209 ivd_ctl_set_config_ip_t *ps_ctl_ip; 3210 ivd_ctl_set_config_op_t *ps_ctl_op; 3211 WORD32 ret = IV_SUCCESS; 3212 UWORD32 subcommand; 3213 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3214 3215 if(ps_dec->init_done != 1) 3216 { 3217 //Return proper Error Code 3218 return IV_FAIL; 3219 } 3220 ps_ctl_ip = (ivd_ctl_set_config_ip_t*)pv_api_ip; 3221 ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op; 3222 ps_ctl_op->u4_error_code = 0; 3223 subcommand = ps_ctl_ip->e_sub_cmd; 3224 3225 switch(subcommand) 3226 { 3227 case IVD_CMD_CTL_GETPARAMS: 3228 ret = ih264d_get_status(dec_hdl, (void *)pv_api_ip, 3229 (void *)pv_api_op); 3230 break; 3231 case IVD_CMD_CTL_SETPARAMS: 3232 ret = ih264d_set_params(dec_hdl, (void *)pv_api_ip, 3233 (void *)pv_api_op); 3234 break; 3235 case IVD_CMD_CTL_RESET: 3236 ret = ih264d_reset(dec_hdl, (void *)pv_api_ip, (void *)pv_api_op); 3237 break; 3238 case IVD_CMD_CTL_SETDEFAULT: 3239 ret = ih264d_set_default_params(dec_hdl, (void *)pv_api_ip, 3240 (void *)pv_api_op); 3241 break; 3242 case IVD_CMD_CTL_FLUSH: 3243 ret = ih264d_set_flush_mode(dec_hdl, (void *)pv_api_ip, 3244 (void *)pv_api_op); 3245 break; 3246 case IVD_CMD_CTL_GETBUFINFO: 3247 ret = ih264d_get_buf_info(dec_hdl, (void *)pv_api_ip, 3248 (void *)pv_api_op); 3249 break; 3250 case IVD_CMD_CTL_GETVERSION: 3251 ret = ih264d_get_version(dec_hdl, (void *)pv_api_ip, 3252 (void *)pv_api_op); 3253 break; 3254 case IH264D_CMD_CTL_DEGRADE: 3255 ret = ih264d_set_degrade(dec_hdl, (void *)pv_api_ip, 3256 (void *)pv_api_op); 3257 break; 3258 3259 case IH264D_CMD_CTL_SET_NUM_CORES: 3260 ret = ih264d_set_num_cores(dec_hdl, (void *)pv_api_ip, 3261 (void *)pv_api_op); 3262 break; 3263 case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS: 3264 ret = ih264d_get_frame_dimensions(dec_hdl, (void *)pv_api_ip, 3265 (void *)pv_api_op); 3266 break; 3267 case IH264D_CMD_CTL_GET_VUI_PARAMS: 3268 ret = ih264d_get_vui_params(dec_hdl, (void *)pv_api_ip, 3269 (void *)pv_api_op); 3270 break; 3271 3272 case IH264D_CMD_CTL_SET_PROCESSOR: 3273 ret = ih264d_set_processor(dec_hdl, (void *)pv_api_ip, 3274 (void *)pv_api_op); 3275 break; 3276 default: 3277 H264_DEC_DEBUG_PRINT("\ndo nothing\n") 3278 ; 3279 break; 3280 } 3281 3282 return ret; 3283 } 3284 /*****************************************************************************/ 3285 /* */ 3286 /* Function Name : ih264d_rel_display_frame */ 3287 /* */ 3288 /* Description : */ 3289 /* */ 3290 /* Inputs :iv_obj_t decoder handle */ 3291 /* :pv_api_ip pointer to input structure */ 3292 /* :pv_api_op pointer to output structure */ 3293 /* Outputs : */ 3294 /* Returns : void */ 3295 /* */ 3296 /* Issues : none */ 3297 /* */ 3298 /* Revision History: */ 3299 /* */ 3300 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3301 /* 22 10 2008 100356 Draft */ 3302 /* */ 3303 /*****************************************************************************/ 3304 WORD32 ih264d_rel_display_frame(iv_obj_t *dec_hdl, 3305 void *pv_api_ip, 3306 void *pv_api_op) 3307 { 3308 3309 ivd_rel_display_frame_ip_t *ps_rel_ip; 3310 ivd_rel_display_frame_op_t *ps_rel_op; 3311 UWORD32 buf_released = 0; 3312 3313 UWORD32 u4_ts = -1; 3314 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3315 3316 ps_rel_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip; 3317 ps_rel_op = (ivd_rel_display_frame_op_t *)pv_api_op; 3318 ps_rel_op->u4_error_code = 0; 3319 u4_ts = ps_rel_ip->u4_disp_buf_id; 3320 3321 if(0 == ps_dec->u4_share_disp_buf) 3322 { 3323 ps_dec->u4_disp_buf_mapping[u4_ts] = 0; 3324 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 0; 3325 return IV_SUCCESS; 3326 } 3327 3328 if(ps_dec->pv_pic_buf_mgr != NULL) 3329 { 3330 if(1 == ps_dec->u4_disp_buf_mapping[u4_ts]) 3331 { 3332 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 3333 ps_rel_ip->u4_disp_buf_id, 3334 BUF_MGR_IO); 3335 ps_dec->u4_disp_buf_mapping[u4_ts] = 0; 3336 buf_released = 1; 3337 } 3338 } 3339 3340 if((1 == ps_dec->u4_share_disp_buf) && (0 == buf_released)) 3341 ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 1; 3342 3343 return IV_SUCCESS; 3344 } 3345 3346 /** 3347 ******************************************************************************* 3348 * 3349 * @brief 3350 * Sets degrade params 3351 * 3352 * @par Description: 3353 * Sets degrade params. 3354 * Refer to ih264d_ctl_degrade_ip_t definition for details 3355 * 3356 * @param[in] ps_codec_obj 3357 * Pointer to codec object at API level 3358 * 3359 * @param[in] pv_api_ip 3360 * Pointer to input argument structure 3361 * 3362 * @param[out] pv_api_op 3363 * Pointer to output argument structure 3364 * 3365 * @returns Status 3366 * 3367 * @remarks 3368 * 3369 * 3370 ******************************************************************************* 3371 */ 3372 3373 WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj, 3374 void *pv_api_ip, 3375 void *pv_api_op) 3376 { 3377 ih264d_ctl_degrade_ip_t *ps_ip; 3378 ih264d_ctl_degrade_op_t *ps_op; 3379 dec_struct_t *ps_codec = (dec_struct_t *)ps_codec_obj->pv_codec_handle; 3380 3381 ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip; 3382 ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op; 3383 3384 ps_codec->i4_degrade_type = ps_ip->i4_degrade_type; 3385 ps_codec->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval; 3386 ps_codec->i4_degrade_pics = ps_ip->i4_degrade_pics; 3387 3388 ps_op->u4_error_code = 0; 3389 ps_codec->i4_degrade_pic_cnt = 0; 3390 3391 return IV_SUCCESS; 3392 } 3393 3394 WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl, 3395 void *pv_api_ip, 3396 void *pv_api_op) 3397 { 3398 ih264d_ctl_get_frame_dimensions_ip_t *ps_ip; 3399 ih264d_ctl_get_frame_dimensions_op_t *ps_op; 3400 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3401 UWORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset; 3402 3403 ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip; 3404 3405 ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op; 3406 UNUSED(ps_ip); 3407 if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid))) 3408 { 3409 disp_wd = ps_dec->u2_disp_width; 3410 disp_ht = ps_dec->u2_disp_height; 3411 3412 if(0 == ps_dec->u4_share_disp_buf) 3413 { 3414 buffer_wd = disp_wd; 3415 buffer_ht = disp_ht; 3416 } 3417 else 3418 { 3419 buffer_wd = ps_dec->u2_frm_wd_y; 3420 buffer_ht = ps_dec->u2_frm_ht_y; 3421 } 3422 } 3423 else 3424 { 3425 disp_wd = 0; 3426 disp_ht = 0; 3427 3428 if(0 == ps_dec->u4_share_disp_buf) 3429 { 3430 buffer_wd = disp_wd; 3431 buffer_ht = disp_ht; 3432 } 3433 else 3434 { 3435 buffer_wd = ALIGN16(disp_wd) + (PAD_LEN_Y_H << 1); 3436 buffer_ht = ALIGN16(disp_ht) + (PAD_LEN_Y_V << 2); 3437 } 3438 } 3439 if(ps_dec->u4_app_disp_width > buffer_wd) 3440 buffer_wd = ps_dec->u4_app_disp_width; 3441 3442 if(0 == ps_dec->u4_share_disp_buf) 3443 { 3444 x_offset = 0; 3445 y_offset = 0; 3446 } 3447 else 3448 { 3449 y_offset = (PAD_LEN_Y_V << 1); 3450 x_offset = PAD_LEN_Y_H; 3451 3452 if((NULL != ps_dec->ps_sps) && (1 == (ps_dec->ps_sps->u1_is_valid)) 3453 && (0 != ps_dec->u2_crop_offset_y)) 3454 { 3455 y_offset += ps_dec->u2_crop_offset_y / ps_dec->u2_frm_wd_y; 3456 x_offset += ps_dec->u2_crop_offset_y % ps_dec->u2_frm_wd_y; 3457 } 3458 } 3459 3460 ps_op->u4_disp_wd[0] = disp_wd; 3461 ps_op->u4_disp_ht[0] = disp_ht; 3462 ps_op->u4_buffer_wd[0] = buffer_wd; 3463 ps_op->u4_buffer_ht[0] = buffer_ht; 3464 ps_op->u4_x_offset[0] = x_offset; 3465 ps_op->u4_y_offset[0] = y_offset; 3466 3467 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1) 3468 >> 1); 3469 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1) 3470 >> 1); 3471 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0] 3472 >> 1); 3473 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0] 3474 >> 1); 3475 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] = 3476 (ps_op->u4_x_offset[0] >> 1); 3477 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] = 3478 (ps_op->u4_y_offset[0] >> 1); 3479 3480 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 3481 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)) 3482 { 3483 ps_op->u4_disp_wd[2] = 0; 3484 ps_op->u4_disp_ht[2] = 0; 3485 ps_op->u4_buffer_wd[2] = 0; 3486 ps_op->u4_buffer_ht[2] = 0; 3487 ps_op->u4_x_offset[2] = 0; 3488 ps_op->u4_y_offset[2] = 0; 3489 3490 ps_op->u4_disp_wd[1] <<= 1; 3491 ps_op->u4_buffer_wd[1] <<= 1; 3492 ps_op->u4_x_offset[1] <<= 1; 3493 } 3494 3495 return IV_SUCCESS; 3496 3497 } 3498 3499 WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl, 3500 void *pv_api_ip, 3501 void *pv_api_op) 3502 { 3503 ih264d_ctl_get_vui_params_ip_t *ps_ip; 3504 ih264d_ctl_get_vui_params_op_t *ps_op; 3505 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3506 dec_seq_params_t *ps_sps; 3507 vui_t *ps_vui; 3508 WORD32 i; 3509 UWORD32 u4_size; 3510 3511 ps_ip = (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip; 3512 ps_op = (ih264d_ctl_get_vui_params_op_t *)pv_api_op; 3513 UNUSED(ps_ip); 3514 3515 u4_size = ps_op->u4_size; 3516 memset(ps_op, 0, sizeof(ih264d_ctl_get_vui_params_op_t)); 3517 ps_op->u4_size = u4_size; 3518 3519 if(NULL == ps_dec->ps_cur_sps) 3520 { 3521 ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND; 3522 return IV_FAIL; 3523 } 3524 3525 ps_sps = ps_dec->ps_cur_sps; 3526 if((0 == ps_sps->u1_is_valid) 3527 || (0 == ps_sps->u1_vui_parameters_present_flag)) 3528 { 3529 ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND; 3530 return IV_FAIL; 3531 } 3532 3533 ps_vui = &ps_sps->s_vui; 3534 3535 ps_op->u1_aspect_ratio_idc = ps_vui->u1_aspect_ratio_idc; 3536 ps_op->u2_sar_width = ps_vui->u2_sar_width; 3537 ps_op->u2_sar_height = ps_vui->u2_sar_height; 3538 ps_op->u1_overscan_appropriate_flag = ps_vui->u1_overscan_appropriate_flag; 3539 ps_op->u1_video_format = ps_vui->u1_video_format; 3540 ps_op->u1_video_full_range_flag = ps_vui->u1_video_full_range_flag; 3541 ps_op->u1_colour_primaries = ps_vui->u1_colour_primaries; 3542 ps_op->u1_tfr_chars = ps_vui->u1_tfr_chars; 3543 ps_op->u1_matrix_coeffs = ps_vui->u1_matrix_coeffs; 3544 ps_op->u1_cr_top_field = ps_vui->u1_cr_top_field; 3545 ps_op->u1_cr_bottom_field = ps_vui->u1_cr_bottom_field; 3546 ps_op->u4_num_units_in_tick = ps_vui->u4_num_units_in_tick; 3547 ps_op->u4_time_scale = ps_vui->u4_time_scale; 3548 ps_op->u1_fixed_frame_rate_flag = ps_vui->u1_fixed_frame_rate_flag; 3549 ps_op->u1_nal_hrd_params_present = ps_vui->u1_nal_hrd_params_present; 3550 ps_op->u1_vcl_hrd_params_present = ps_vui->u1_vcl_hrd_params_present; 3551 ps_op->u1_low_delay_hrd_flag = ps_vui->u1_low_delay_hrd_flag; 3552 ps_op->u1_pic_struct_present_flag = ps_vui->u1_pic_struct_present_flag; 3553 ps_op->u1_bitstream_restriction_flag = ps_vui->u1_bitstream_restriction_flag; 3554 ps_op->u1_mv_over_pic_boundaries_flag = ps_vui->u1_mv_over_pic_boundaries_flag; 3555 ps_op->u4_max_bytes_per_pic_denom = ps_vui->u4_max_bytes_per_pic_denom; 3556 ps_op->u4_max_bits_per_mb_denom = ps_vui->u4_max_bits_per_mb_denom; 3557 ps_op->u4_log2_max_mv_length_horz = ps_vui->u4_log2_max_mv_length_horz; 3558 ps_op->u4_log2_max_mv_length_vert = ps_vui->u4_log2_max_mv_length_vert; 3559 ps_op->u4_num_reorder_frames = ps_vui->u4_num_reorder_frames; 3560 ps_op->u4_max_dec_frame_buffering = ps_vui->u4_max_dec_frame_buffering; 3561 3562 return IV_SUCCESS; 3563 } 3564 3565 WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op) 3566 { 3567 ih264d_ctl_set_num_cores_ip_t *ps_ip; 3568 ih264d_ctl_set_num_cores_op_t *ps_op; 3569 dec_struct_t *ps_dec = dec_hdl->pv_codec_handle; 3570 3571 ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip; 3572 ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op; 3573 ps_op->u4_error_code = 0; 3574 ps_dec->u4_num_cores = ps_ip->u4_num_cores; 3575 if(ps_dec->u4_num_cores == 1) 3576 { 3577 ps_dec->u1_separate_parse = 0; 3578 } 3579 else 3580 { 3581 ps_dec->u1_separate_parse = 1; 3582 } 3583 3584 /*using only upto three threads currently*/ 3585 if(ps_dec->u4_num_cores > 3) 3586 ps_dec->u4_num_cores = 3; 3587 3588 return IV_SUCCESS; 3589 } 3590 3591 void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec, 3592 ivd_video_decode_op_t *ps_dec_op) 3593 { 3594 if((ps_dec_op->u4_error_code & 0xff) 3595 != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED) 3596 { 3597 ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width; 3598 ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height; 3599 } 3600 ps_dec_op->e_pic_type = ps_dec->i4_frametype; 3601 3602 ps_dec_op->u4_new_seq = 0; 3603 ps_dec_op->u4_output_present = ps_dec->u4_output_present; 3604 ps_dec_op->u4_progressive_frame_flag = 3605 ps_dec->s_disp_op.u4_progressive_frame_flag; 3606 3607 ps_dec_op->u4_is_ref_flag = 1; 3608 if(ps_dec_op->u4_frame_decoded_flag) 3609 { 3610 if(ps_dec->ps_cur_slice->u1_nal_ref_idc == 0) 3611 ps_dec_op->u4_is_ref_flag = 0; 3612 } 3613 3614 ps_dec_op->e_output_format = ps_dec->s_disp_op.e_output_format; 3615 ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf; 3616 ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type; 3617 ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts; 3618 ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id; 3619 } 3620 3621 /*****************************************************************************/ 3622 /* */ 3623 /* Function Name : ih264d_api_function */ 3624 /* */ 3625 /* Description : */ 3626 /* */ 3627 /* Inputs :iv_obj_t decoder handle */ 3628 /* :pv_api_ip pointer to input structure */ 3629 /* :pv_api_op pointer to output structure */ 3630 /* Outputs : */ 3631 /* Returns : void */ 3632 /* */ 3633 /* Issues : none */ 3634 /* */ 3635 /* Revision History: */ 3636 /* */ 3637 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 3638 /* 22 10 2008 100356 Draft */ 3639 /* */ 3640 /*****************************************************************************/ 3641 IV_API_CALL_STATUS_T ih264d_api_function(iv_obj_t *dec_hdl, 3642 void *pv_api_ip, 3643 void *pv_api_op) 3644 { 3645 UWORD32 command; 3646 UWORD32 *pu2_ptr_cmd; 3647 UWORD32 u4_api_ret; 3648 IV_API_CALL_STATUS_T e_status; 3649 e_status = api_check_struct_sanity(dec_hdl, pv_api_ip, pv_api_op); 3650 3651 if(e_status != IV_SUCCESS) 3652 { 3653 UWORD32 *ptr_err; 3654 3655 ptr_err = (UWORD32 *)pv_api_op; 3656 UNUSED(ptr_err); 3657 H264_DEC_DEBUG_PRINT("error code = %d\n", *(ptr_err + 1)); 3658 return IV_FAIL; 3659 } 3660 3661 pu2_ptr_cmd = (UWORD32 *)pv_api_ip; 3662 pu2_ptr_cmd++; 3663 3664 command = *pu2_ptr_cmd; 3665 // H264_DEC_DEBUG_PRINT("inside lib = %d\n",command); 3666 switch(command) 3667 { 3668 3669 case IVD_CMD_CREATE: 3670 u4_api_ret = ih264d_create(dec_hdl, (void *)pv_api_ip, 3671 (void *)pv_api_op); 3672 break; 3673 case IVD_CMD_DELETE: 3674 u4_api_ret = ih264d_delete(dec_hdl, (void *)pv_api_ip, 3675 (void *)pv_api_op); 3676 break; 3677 3678 case IVD_CMD_VIDEO_DECODE: 3679 u4_api_ret = ih264d_video_decode(dec_hdl, (void *)pv_api_ip, 3680 (void *)pv_api_op); 3681 break; 3682 3683 case IVD_CMD_GET_DISPLAY_FRAME: 3684 u4_api_ret = ih264d_get_display_frame(dec_hdl, (void *)pv_api_ip, 3685 (void *)pv_api_op); 3686 3687 break; 3688 3689 case IVD_CMD_SET_DISPLAY_FRAME: 3690 u4_api_ret = ih264d_set_display_frame(dec_hdl, (void *)pv_api_ip, 3691 (void *)pv_api_op); 3692 3693 break; 3694 3695 case IVD_CMD_REL_DISPLAY_FRAME: 3696 u4_api_ret = ih264d_rel_display_frame(dec_hdl, (void *)pv_api_ip, 3697 (void *)pv_api_op); 3698 break; 3699 3700 case IVD_CMD_VIDEO_CTL: 3701 u4_api_ret = ih264d_ctl(dec_hdl, (void *)pv_api_ip, 3702 (void *)pv_api_op); 3703 break; 3704 default: 3705 u4_api_ret = IV_FAIL; 3706 break; 3707 } 3708 3709 return u4_api_ret; 3710 } 3711
