1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Christian Knig <christian.koenig (at) amd.com> 25 */ 26 27 #include "util/u_memory.h" 28 #include "util/u_framebuffer.h" 29 #include "util/u_blitter.h" 30 #include "util/u_pack_color.h" 31 #include "tgsi/tgsi_parse.h" 32 #include "radeonsi_pipe.h" 33 #include "radeonsi_shader.h" 34 #include "si_state.h" 35 #include "sid.h" 36 37 /* 38 * inferred framebuffer and blender state 39 */ 40 static void si_update_fb_blend_state(struct r600_context *rctx) 41 { 42 struct si_pm4_state *pm4; 43 struct si_state_blend *blend = rctx->queued.named.blend; 44 uint32_t mask; 45 46 if (blend == NULL) 47 return; 48 49 pm4 = CALLOC_STRUCT(si_pm4_state); 50 if (pm4 == NULL) 51 return; 52 53 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1; 54 mask &= blend->cb_target_mask; 55 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask); 56 57 si_pm4_set_state(rctx, fb_blend, pm4); 58 } 59 60 /* 61 * Blender functions 62 */ 63 64 static uint32_t si_translate_blend_function(int blend_func) 65 { 66 switch (blend_func) { 67 case PIPE_BLEND_ADD: 68 return V_028780_COMB_DST_PLUS_SRC; 69 case PIPE_BLEND_SUBTRACT: 70 return V_028780_COMB_SRC_MINUS_DST; 71 case PIPE_BLEND_REVERSE_SUBTRACT: 72 return V_028780_COMB_DST_MINUS_SRC; 73 case PIPE_BLEND_MIN: 74 return V_028780_COMB_MIN_DST_SRC; 75 case PIPE_BLEND_MAX: 76 return V_028780_COMB_MAX_DST_SRC; 77 default: 78 R600_ERR("Unknown blend function %d\n", blend_func); 79 assert(0); 80 break; 81 } 82 return 0; 83 } 84 85 static uint32_t si_translate_blend_factor(int blend_fact) 86 { 87 switch (blend_fact) { 88 case PIPE_BLENDFACTOR_ONE: 89 return V_028780_BLEND_ONE; 90 case PIPE_BLENDFACTOR_SRC_COLOR: 91 return V_028780_BLEND_SRC_COLOR; 92 case PIPE_BLENDFACTOR_SRC_ALPHA: 93 return V_028780_BLEND_SRC_ALPHA; 94 case PIPE_BLENDFACTOR_DST_ALPHA: 95 return V_028780_BLEND_DST_ALPHA; 96 case PIPE_BLENDFACTOR_DST_COLOR: 97 return V_028780_BLEND_DST_COLOR; 98 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 99 return V_028780_BLEND_SRC_ALPHA_SATURATE; 100 case PIPE_BLENDFACTOR_CONST_COLOR: 101 return V_028780_BLEND_CONSTANT_COLOR; 102 case PIPE_BLENDFACTOR_CONST_ALPHA: 103 return V_028780_BLEND_CONSTANT_ALPHA; 104 case PIPE_BLENDFACTOR_ZERO: 105 return V_028780_BLEND_ZERO; 106 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 107 return V_028780_BLEND_ONE_MINUS_SRC_COLOR; 108 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 109 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA; 110 case PIPE_BLENDFACTOR_INV_DST_ALPHA: 111 return V_028780_BLEND_ONE_MINUS_DST_ALPHA; 112 case PIPE_BLENDFACTOR_INV_DST_COLOR: 113 return V_028780_BLEND_ONE_MINUS_DST_COLOR; 114 case PIPE_BLENDFACTOR_INV_CONST_COLOR: 115 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR; 116 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: 117 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA; 118 case PIPE_BLENDFACTOR_SRC1_COLOR: 119 return V_028780_BLEND_SRC1_COLOR; 120 case PIPE_BLENDFACTOR_SRC1_ALPHA: 121 return V_028780_BLEND_SRC1_ALPHA; 122 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: 123 return V_028780_BLEND_INV_SRC1_COLOR; 124 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: 125 return V_028780_BLEND_INV_SRC1_ALPHA; 126 default: 127 R600_ERR("Bad blend factor %d not supported!\n", blend_fact); 128 assert(0); 129 break; 130 } 131 return 0; 132 } 133 134 static void *si_create_blend_state(struct pipe_context *ctx, 135 const struct pipe_blend_state *state) 136 { 137 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend); 138 struct si_pm4_state *pm4 = &blend->pm4; 139 140 uint32_t color_control; 141 142 if (blend == NULL) 143 return NULL; 144 145 color_control = S_028808_MODE(V_028808_CB_NORMAL); 146 if (state->logicop_enable) { 147 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4)); 148 } else { 149 color_control |= S_028808_ROP3(0xcc); 150 } 151 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control); 152 153 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0); 154 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0); 155 156 blend->cb_target_mask = 0; 157 for (int i = 0; i < 8; i++) { 158 /* state->rt entries > 0 only written if independent blending */ 159 const int j = state->independent_blend_enable ? i : 0; 160 161 unsigned eqRGB = state->rt[j].rgb_func; 162 unsigned srcRGB = state->rt[j].rgb_src_factor; 163 unsigned dstRGB = state->rt[j].rgb_dst_factor; 164 unsigned eqA = state->rt[j].alpha_func; 165 unsigned srcA = state->rt[j].alpha_src_factor; 166 unsigned dstA = state->rt[j].alpha_dst_factor; 167 168 unsigned blend_cntl = 0; 169 170 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 171 blend->cb_target_mask |= state->rt[j].colormask << (4 * i); 172 173 if (!state->rt[j].blend_enable) { 174 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); 175 continue; 176 } 177 178 blend_cntl |= S_028780_ENABLE(1); 179 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB)); 180 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB)); 181 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB)); 182 183 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 184 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1); 185 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA)); 186 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA)); 187 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA)); 188 } 189 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); 190 } 191 192 return blend; 193 } 194 195 static void si_bind_blend_state(struct pipe_context *ctx, void *state) 196 { 197 struct r600_context *rctx = (struct r600_context *)ctx; 198 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state); 199 si_update_fb_blend_state(rctx); 200 } 201 202 static void si_delete_blend_state(struct pipe_context *ctx, void *state) 203 { 204 struct r600_context *rctx = (struct r600_context *)ctx; 205 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state); 206 } 207 208 static void si_set_blend_color(struct pipe_context *ctx, 209 const struct pipe_blend_color *state) 210 { 211 struct r600_context *rctx = (struct r600_context *)ctx; 212 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 213 214 if (pm4 == NULL) 215 return; 216 217 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0])); 218 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1])); 219 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2])); 220 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3])); 221 222 si_pm4_set_state(rctx, blend_color, pm4); 223 } 224 225 /* 226 * Clipping, scissors and viewport 227 */ 228 229 static void si_set_clip_state(struct pipe_context *ctx, 230 const struct pipe_clip_state *state) 231 { 232 struct r600_context *rctx = (struct r600_context *)ctx; 233 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 234 235 if (pm4 == NULL) 236 return; 237 238 for (int i = 0; i < 6; i++) { 239 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16, 240 fui(state->ucp[i][0])); 241 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16, 242 fui(state->ucp[i][1])); 243 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16, 244 fui(state->ucp[i][2])); 245 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16, 246 fui(state->ucp[i][3])); 247 } 248 249 si_pm4_set_state(rctx, clip, pm4); 250 } 251 252 static void si_set_scissor_state(struct pipe_context *ctx, 253 const struct pipe_scissor_state *state) 254 { 255 struct r600_context *rctx = (struct r600_context *)ctx; 256 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 257 uint32_t tl, br; 258 259 if (pm4 == NULL) 260 return; 261 262 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny); 263 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); 264 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl); 265 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br); 266 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl); 267 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br); 268 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl); 269 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br); 270 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl); 271 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br); 272 273 si_pm4_set_state(rctx, scissor, pm4); 274 } 275 276 static void si_set_viewport_state(struct pipe_context *ctx, 277 const struct pipe_viewport_state *state) 278 { 279 struct r600_context *rctx = (struct r600_context *)ctx; 280 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport); 281 struct si_pm4_state *pm4 = &viewport->pm4; 282 283 if (viewport == NULL) 284 return; 285 286 viewport->viewport = *state; 287 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000); 288 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000); 289 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0])); 290 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0])); 291 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1])); 292 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1])); 293 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2])); 294 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2])); 295 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F); 296 297 si_pm4_set_state(rctx, viewport, viewport); 298 } 299 300 /* 301 * inferred state between framebuffer and rasterizer 302 */ 303 static void si_update_fb_rs_state(struct r600_context *rctx) 304 { 305 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer; 306 struct si_pm4_state *pm4; 307 unsigned offset_db_fmt_cntl = 0, depth; 308 float offset_units; 309 310 if (!rs || !rctx->framebuffer.zsbuf) 311 return; 312 313 offset_units = rctx->queued.named.rasterizer->offset_units; 314 switch (rctx->framebuffer.zsbuf->texture->format) { 315 case PIPE_FORMAT_Z24X8_UNORM: 316 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 317 depth = -24; 318 offset_units *= 2.0f; 319 break; 320 case PIPE_FORMAT_Z32_FLOAT: 321 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 322 depth = -23; 323 offset_units *= 1.0f; 324 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 325 break; 326 case PIPE_FORMAT_Z16_UNORM: 327 depth = -16; 328 offset_units *= 4.0f; 329 break; 330 default: 331 return; 332 } 333 334 pm4 = CALLOC_STRUCT(si_pm4_state); 335 /* FIXME some of those reg can be computed with cso */ 336 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth); 337 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 338 fui(rctx->queued.named.rasterizer->offset_scale)); 339 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units)); 340 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 341 fui(rctx->queued.named.rasterizer->offset_scale)); 342 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units)); 343 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl); 344 345 si_pm4_set_state(rctx, fb_rs, pm4); 346 } 347 348 /* 349 * Rasterizer 350 */ 351 352 static uint32_t si_translate_fill(uint32_t func) 353 { 354 switch(func) { 355 case PIPE_POLYGON_MODE_FILL: 356 return V_028814_X_DRAW_TRIANGLES; 357 case PIPE_POLYGON_MODE_LINE: 358 return V_028814_X_DRAW_LINES; 359 case PIPE_POLYGON_MODE_POINT: 360 return V_028814_X_DRAW_POINTS; 361 default: 362 assert(0); 363 return V_028814_X_DRAW_POINTS; 364 } 365 } 366 367 static void *si_create_rs_state(struct pipe_context *ctx, 368 const struct pipe_rasterizer_state *state) 369 { 370 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer); 371 struct si_pm4_state *pm4 = &rs->pm4; 372 unsigned tmp; 373 unsigned prov_vtx = 1, polygon_dual_mode; 374 unsigned clip_rule; 375 float psize_min, psize_max; 376 377 if (rs == NULL) { 378 return NULL; 379 } 380 381 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || 382 state->fill_back != PIPE_POLYGON_MODE_FILL); 383 384 if (state->flatshade_first) 385 prov_vtx = 0; 386 387 rs->flatshade = state->flatshade; 388 rs->sprite_coord_enable = state->sprite_coord_enable; 389 rs->pa_sc_line_stipple = state->line_stipple_enable ? 390 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | 391 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; 392 rs->pa_su_sc_mode_cntl = 393 S_028814_PROVOKING_VTX_LAST(prov_vtx) | 394 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | 395 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | 396 S_028814_FACE(!state->front_ccw) | 397 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | 398 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | 399 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | 400 S_028814_POLY_MODE(polygon_dual_mode) | 401 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) | 402 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)); 403 rs->pa_cl_clip_cntl = 404 S_028810_PS_UCP_MODE(3) | 405 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | 406 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | 407 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); 408 rs->pa_cl_vs_out_cntl = 409 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) | 410 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex); 411 412 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 413 414 /* offset */ 415 rs->offset_units = state->offset_units; 416 rs->offset_scale = state->offset_scale * 12.0f; 417 418 /* XXX: Flat shading hangs the GPU */ 419 tmp = S_0286D4_FLAT_SHADE_ENA(0); 420 if (state->sprite_coord_enable) { 421 tmp |= S_0286D4_PNT_SPRITE_ENA(1) | 422 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) | 423 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) | 424 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) | 425 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1); 426 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { 427 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); 428 } 429 } 430 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp); 431 432 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000); 433 /* point size 12.4 fixed point */ 434 tmp = (unsigned)(state->point_size * 8.0); 435 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); 436 437 if (state->point_size_per_vertex) { 438 psize_min = util_get_min_point_size(state); 439 psize_max = 8192; 440 } else { 441 /* Force the point size to be as if the vertex output was disabled. */ 442 psize_min = state->point_size; 443 psize_max = state->point_size; 444 } 445 /* Divide by two, because 0.5 = 1 pixel. */ 446 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX, 447 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | 448 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2))); 449 450 tmp = (unsigned)state->line_width * 8; 451 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp)); 452 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0, 453 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable)); 454 455 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400); 456 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL, 457 S_028BE4_PIX_CENTER(state->gl_rasterization_rules)); 458 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000); 459 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000); 460 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000); 461 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000); 462 463 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); 464 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule); 465 466 return rs; 467 } 468 469 static void si_bind_rs_state(struct pipe_context *ctx, void *state) 470 { 471 struct r600_context *rctx = (struct r600_context *)ctx; 472 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state; 473 474 if (state == NULL) 475 return; 476 477 // TODO 478 rctx->sprite_coord_enable = rs->sprite_coord_enable; 479 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple; 480 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl; 481 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl; 482 rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl; 483 484 si_pm4_bind_state(rctx, rasterizer, rs); 485 si_update_fb_rs_state(rctx); 486 } 487 488 static void si_delete_rs_state(struct pipe_context *ctx, void *state) 489 { 490 struct r600_context *rctx = (struct r600_context *)ctx; 491 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state); 492 } 493 494 /* 495 * infeered state between dsa and stencil ref 496 */ 497 static void si_update_dsa_stencil_ref(struct r600_context *rctx) 498 { 499 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 500 struct pipe_stencil_ref *ref = &rctx->stencil_ref; 501 struct si_state_dsa *dsa = rctx->queued.named.dsa; 502 503 if (pm4 == NULL) 504 return; 505 506 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK, 507 S_028430_STENCILTESTVAL(ref->ref_value[0]) | 508 S_028430_STENCILMASK(dsa->valuemask[0]) | 509 S_028430_STENCILWRITEMASK(dsa->writemask[0])); 510 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF, 511 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) | 512 S_028434_STENCILMASK_BF(dsa->valuemask[1]) | 513 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1])); 514 515 si_pm4_set_state(rctx, dsa_stencil_ref, pm4); 516 } 517 518 static void si_set_pipe_stencil_ref(struct pipe_context *ctx, 519 const struct pipe_stencil_ref *state) 520 { 521 struct r600_context *rctx = (struct r600_context *)ctx; 522 rctx->stencil_ref = *state; 523 si_update_dsa_stencil_ref(rctx); 524 } 525 526 527 /* 528 * DSA 529 */ 530 531 static uint32_t si_translate_stencil_op(int s_op) 532 { 533 switch (s_op) { 534 case PIPE_STENCIL_OP_KEEP: 535 return V_02842C_STENCIL_KEEP; 536 case PIPE_STENCIL_OP_ZERO: 537 return V_02842C_STENCIL_ZERO; 538 case PIPE_STENCIL_OP_REPLACE: 539 return V_02842C_STENCIL_REPLACE_TEST; 540 case PIPE_STENCIL_OP_INCR: 541 return V_02842C_STENCIL_ADD_CLAMP; 542 case PIPE_STENCIL_OP_DECR: 543 return V_02842C_STENCIL_SUB_CLAMP; 544 case PIPE_STENCIL_OP_INCR_WRAP: 545 return V_02842C_STENCIL_ADD_WRAP; 546 case PIPE_STENCIL_OP_DECR_WRAP: 547 return V_02842C_STENCIL_SUB_WRAP; 548 case PIPE_STENCIL_OP_INVERT: 549 return V_02842C_STENCIL_INVERT; 550 default: 551 R600_ERR("Unknown stencil op %d", s_op); 552 assert(0); 553 break; 554 } 555 return 0; 556 } 557 558 static void *si_create_dsa_state(struct pipe_context *ctx, 559 const struct pipe_depth_stencil_alpha_state *state) 560 { 561 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa); 562 struct si_pm4_state *pm4 = &dsa->pm4; 563 unsigned db_depth_control, /* alpha_test_control, */ alpha_ref; 564 unsigned db_render_override, db_render_control; 565 uint32_t db_stencil_control = 0; 566 567 if (dsa == NULL) { 568 return NULL; 569 } 570 571 dsa->valuemask[0] = state->stencil[0].valuemask; 572 dsa->valuemask[1] = state->stencil[1].valuemask; 573 dsa->writemask[0] = state->stencil[0].writemask; 574 dsa->writemask[1] = state->stencil[1].writemask; 575 576 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 577 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 578 S_028800_ZFUNC(state->depth.func); 579 580 /* stencil */ 581 if (state->stencil[0].enabled) { 582 db_depth_control |= S_028800_STENCIL_ENABLE(1); 583 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); 584 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op)); 585 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op)); 586 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op)); 587 588 if (state->stencil[1].enabled) { 589 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 590 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); 591 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op)); 592 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op)); 593 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op)); 594 } 595 } 596 597 /* alpha */ 598 //alpha_test_control = 0; 599 alpha_ref = 0; 600 if (state->alpha.enabled) { 601 //alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); 602 //alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); 603 alpha_ref = fui(state->alpha.ref_value); 604 } 605 dsa->alpha_ref = alpha_ref; 606 607 /* misc */ 608 db_render_control = 0; 609 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) | 610 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | 611 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE); 612 /* TODO db_render_override depends on query */ 613 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000); 614 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000); 615 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000); 616 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000); 617 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control); 618 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control); 619 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control); 620 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override); 621 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control); 622 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0); 623 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0); 624 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0); 625 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00); 626 dsa->db_render_override = db_render_override; 627 628 return dsa; 629 } 630 631 static void si_bind_dsa_state(struct pipe_context *ctx, void *state) 632 { 633 struct r600_context *rctx = (struct r600_context *)ctx; 634 struct si_state_dsa *dsa = state; 635 636 if (state == NULL) 637 return; 638 639 si_pm4_bind_state(rctx, dsa, dsa); 640 si_update_dsa_stencil_ref(rctx); 641 642 // TODO 643 rctx->alpha_ref = dsa->alpha_ref; 644 rctx->alpha_ref_dirty = true; 645 } 646 647 static void si_delete_dsa_state(struct pipe_context *ctx, void *state) 648 { 649 struct r600_context *rctx = (struct r600_context *)ctx; 650 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state); 651 } 652 653 static void *si_create_db_flush_dsa(struct r600_context *rctx) 654 { 655 struct pipe_depth_stencil_alpha_state dsa; 656 struct si_state_dsa *state; 657 658 memset(&dsa, 0, sizeof(dsa)); 659 660 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa); 661 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL, 662 S_028000_DEPTH_COPY(1) | 663 S_028000_STENCIL_COPY(1) | 664 S_028000_COPY_CENTROID(1)); 665 return state; 666 } 667 668 /* 669 * format translation 670 */ 671 static uint32_t si_translate_colorformat(enum pipe_format format) 672 { 673 switch (format) { 674 /* 8-bit buffers. */ 675 case PIPE_FORMAT_A8_UNORM: 676 case PIPE_FORMAT_A8_UINT: 677 case PIPE_FORMAT_A8_SINT: 678 case PIPE_FORMAT_I8_UNORM: 679 case PIPE_FORMAT_I8_UINT: 680 case PIPE_FORMAT_I8_SINT: 681 case PIPE_FORMAT_L8_UNORM: 682 case PIPE_FORMAT_L8_UINT: 683 case PIPE_FORMAT_L8_SINT: 684 case PIPE_FORMAT_L8_SRGB: 685 case PIPE_FORMAT_R8_UNORM: 686 case PIPE_FORMAT_R8_SNORM: 687 case PIPE_FORMAT_R8_UINT: 688 case PIPE_FORMAT_R8_SINT: 689 return V_028C70_COLOR_8; 690 691 /* 16-bit buffers. */ 692 case PIPE_FORMAT_B5G6R5_UNORM: 693 return V_028C70_COLOR_5_6_5; 694 695 case PIPE_FORMAT_B5G5R5A1_UNORM: 696 case PIPE_FORMAT_B5G5R5X1_UNORM: 697 return V_028C70_COLOR_1_5_5_5; 698 699 case PIPE_FORMAT_B4G4R4A4_UNORM: 700 case PIPE_FORMAT_B4G4R4X4_UNORM: 701 return V_028C70_COLOR_4_4_4_4; 702 703 case PIPE_FORMAT_L8A8_UNORM: 704 case PIPE_FORMAT_L8A8_UINT: 705 case PIPE_FORMAT_L8A8_SINT: 706 case PIPE_FORMAT_L8A8_SRGB: 707 case PIPE_FORMAT_R8G8_UNORM: 708 case PIPE_FORMAT_R8G8_UINT: 709 case PIPE_FORMAT_R8G8_SINT: 710 return V_028C70_COLOR_8_8; 711 712 case PIPE_FORMAT_Z16_UNORM: 713 case PIPE_FORMAT_R16_UNORM: 714 case PIPE_FORMAT_R16_UINT: 715 case PIPE_FORMAT_R16_SINT: 716 case PIPE_FORMAT_R16_FLOAT: 717 case PIPE_FORMAT_R16G16_FLOAT: 718 return V_028C70_COLOR_16; 719 720 /* 32-bit buffers. */ 721 case PIPE_FORMAT_A8B8G8R8_SRGB: 722 case PIPE_FORMAT_A8B8G8R8_UNORM: 723 case PIPE_FORMAT_A8R8G8B8_UNORM: 724 case PIPE_FORMAT_B8G8R8A8_SRGB: 725 case PIPE_FORMAT_B8G8R8A8_UNORM: 726 case PIPE_FORMAT_B8G8R8X8_UNORM: 727 case PIPE_FORMAT_R8G8B8A8_SNORM: 728 case PIPE_FORMAT_R8G8B8A8_UNORM: 729 case PIPE_FORMAT_R8G8B8X8_UNORM: 730 case PIPE_FORMAT_R8SG8SB8UX8U_NORM: 731 case PIPE_FORMAT_X8B8G8R8_UNORM: 732 case PIPE_FORMAT_X8R8G8B8_UNORM: 733 case PIPE_FORMAT_R8G8B8_UNORM: 734 case PIPE_FORMAT_R8G8B8A8_SSCALED: 735 case PIPE_FORMAT_R8G8B8A8_USCALED: 736 case PIPE_FORMAT_R8G8B8A8_SINT: 737 case PIPE_FORMAT_R8G8B8A8_UINT: 738 return V_028C70_COLOR_8_8_8_8; 739 740 case PIPE_FORMAT_R10G10B10A2_UNORM: 741 case PIPE_FORMAT_R10G10B10X2_SNORM: 742 case PIPE_FORMAT_B10G10R10A2_UNORM: 743 case PIPE_FORMAT_B10G10R10A2_UINT: 744 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 745 return V_028C70_COLOR_2_10_10_10; 746 747 case PIPE_FORMAT_Z24X8_UNORM: 748 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 749 return V_028C70_COLOR_8_24; 750 751 case PIPE_FORMAT_X8Z24_UNORM: 752 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 753 return V_028C70_COLOR_24_8; 754 755 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 756 return V_028C70_COLOR_X24_8_32_FLOAT; 757 758 case PIPE_FORMAT_R32_FLOAT: 759 case PIPE_FORMAT_Z32_FLOAT: 760 return V_028C70_COLOR_32; 761 762 case PIPE_FORMAT_R16G16_SSCALED: 763 case PIPE_FORMAT_R16G16_UNORM: 764 case PIPE_FORMAT_R16G16_UINT: 765 case PIPE_FORMAT_R16G16_SINT: 766 return V_028C70_COLOR_16_16; 767 768 case PIPE_FORMAT_R11G11B10_FLOAT: 769 return V_028C70_COLOR_10_11_11; 770 771 /* 64-bit buffers. */ 772 case PIPE_FORMAT_R16G16B16_USCALED: 773 case PIPE_FORMAT_R16G16B16_SSCALED: 774 case PIPE_FORMAT_R16G16B16A16_UINT: 775 case PIPE_FORMAT_R16G16B16A16_SINT: 776 case PIPE_FORMAT_R16G16B16A16_USCALED: 777 case PIPE_FORMAT_R16G16B16A16_SSCALED: 778 case PIPE_FORMAT_R16G16B16A16_UNORM: 779 case PIPE_FORMAT_R16G16B16A16_SNORM: 780 case PIPE_FORMAT_R16G16B16_FLOAT: 781 case PIPE_FORMAT_R16G16B16A16_FLOAT: 782 return V_028C70_COLOR_16_16_16_16; 783 784 case PIPE_FORMAT_R32G32_FLOAT: 785 case PIPE_FORMAT_R32G32_USCALED: 786 case PIPE_FORMAT_R32G32_SSCALED: 787 case PIPE_FORMAT_R32G32_SINT: 788 case PIPE_FORMAT_R32G32_UINT: 789 return V_028C70_COLOR_32_32; 790 791 /* 128-bit buffers. */ 792 case PIPE_FORMAT_R32G32B32A32_SNORM: 793 case PIPE_FORMAT_R32G32B32A32_UNORM: 794 case PIPE_FORMAT_R32G32B32A32_SSCALED: 795 case PIPE_FORMAT_R32G32B32A32_USCALED: 796 case PIPE_FORMAT_R32G32B32A32_SINT: 797 case PIPE_FORMAT_R32G32B32A32_UINT: 798 case PIPE_FORMAT_R32G32B32A32_FLOAT: 799 return V_028C70_COLOR_32_32_32_32; 800 801 /* YUV buffers. */ 802 case PIPE_FORMAT_UYVY: 803 case PIPE_FORMAT_YUYV: 804 /* 96-bit buffers. */ 805 case PIPE_FORMAT_R32G32B32_FLOAT: 806 /* 8-bit buffers. */ 807 case PIPE_FORMAT_L4A4_UNORM: 808 case PIPE_FORMAT_R4A4_UNORM: 809 case PIPE_FORMAT_A4R4_UNORM: 810 default: 811 return ~0U; /* Unsupported. */ 812 } 813 } 814 815 static uint32_t si_translate_colorswap(enum pipe_format format) 816 { 817 switch (format) { 818 /* 8-bit buffers. */ 819 case PIPE_FORMAT_L4A4_UNORM: 820 case PIPE_FORMAT_A4R4_UNORM: 821 return V_028C70_SWAP_ALT; 822 823 case PIPE_FORMAT_A8_UNORM: 824 case PIPE_FORMAT_A8_UINT: 825 case PIPE_FORMAT_A8_SINT: 826 case PIPE_FORMAT_R4A4_UNORM: 827 return V_028C70_SWAP_ALT_REV; 828 case PIPE_FORMAT_I8_UNORM: 829 case PIPE_FORMAT_L8_UNORM: 830 case PIPE_FORMAT_I8_UINT: 831 case PIPE_FORMAT_I8_SINT: 832 case PIPE_FORMAT_L8_UINT: 833 case PIPE_FORMAT_L8_SINT: 834 case PIPE_FORMAT_L8_SRGB: 835 case PIPE_FORMAT_R8_UNORM: 836 case PIPE_FORMAT_R8_SNORM: 837 case PIPE_FORMAT_R8_UINT: 838 case PIPE_FORMAT_R8_SINT: 839 return V_028C70_SWAP_STD; 840 841 /* 16-bit buffers. */ 842 case PIPE_FORMAT_B5G6R5_UNORM: 843 return V_028C70_SWAP_STD_REV; 844 845 case PIPE_FORMAT_B5G5R5A1_UNORM: 846 case PIPE_FORMAT_B5G5R5X1_UNORM: 847 return V_028C70_SWAP_ALT; 848 849 case PIPE_FORMAT_B4G4R4A4_UNORM: 850 case PIPE_FORMAT_B4G4R4X4_UNORM: 851 return V_028C70_SWAP_ALT; 852 853 case PIPE_FORMAT_Z16_UNORM: 854 return V_028C70_SWAP_STD; 855 856 case PIPE_FORMAT_L8A8_UNORM: 857 case PIPE_FORMAT_L8A8_UINT: 858 case PIPE_FORMAT_L8A8_SINT: 859 case PIPE_FORMAT_L8A8_SRGB: 860 return V_028C70_SWAP_ALT; 861 case PIPE_FORMAT_R8G8_UNORM: 862 case PIPE_FORMAT_R8G8_UINT: 863 case PIPE_FORMAT_R8G8_SINT: 864 return V_028C70_SWAP_STD; 865 866 case PIPE_FORMAT_R16_UNORM: 867 case PIPE_FORMAT_R16_UINT: 868 case PIPE_FORMAT_R16_SINT: 869 case PIPE_FORMAT_R16_FLOAT: 870 return V_028C70_SWAP_STD; 871 872 /* 32-bit buffers. */ 873 case PIPE_FORMAT_A8B8G8R8_SRGB: 874 return V_028C70_SWAP_STD_REV; 875 case PIPE_FORMAT_B8G8R8A8_SRGB: 876 return V_028C70_SWAP_ALT; 877 878 case PIPE_FORMAT_B8G8R8A8_UNORM: 879 case PIPE_FORMAT_B8G8R8X8_UNORM: 880 return V_028C70_SWAP_ALT; 881 882 case PIPE_FORMAT_A8R8G8B8_UNORM: 883 case PIPE_FORMAT_X8R8G8B8_UNORM: 884 return V_028C70_SWAP_ALT_REV; 885 case PIPE_FORMAT_R8G8B8A8_SNORM: 886 case PIPE_FORMAT_R8G8B8A8_UNORM: 887 case PIPE_FORMAT_R8G8B8A8_SSCALED: 888 case PIPE_FORMAT_R8G8B8A8_USCALED: 889 case PIPE_FORMAT_R8G8B8A8_SINT: 890 case PIPE_FORMAT_R8G8B8A8_UINT: 891 case PIPE_FORMAT_R8G8B8X8_UNORM: 892 return V_028C70_SWAP_STD; 893 894 case PIPE_FORMAT_A8B8G8R8_UNORM: 895 case PIPE_FORMAT_X8B8G8R8_UNORM: 896 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */ 897 return V_028C70_SWAP_STD_REV; 898 899 case PIPE_FORMAT_Z24X8_UNORM: 900 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 901 return V_028C70_SWAP_STD; 902 903 case PIPE_FORMAT_X8Z24_UNORM: 904 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 905 return V_028C70_SWAP_STD; 906 907 case PIPE_FORMAT_R10G10B10A2_UNORM: 908 case PIPE_FORMAT_R10G10B10X2_SNORM: 909 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 910 return V_028C70_SWAP_STD; 911 912 case PIPE_FORMAT_B10G10R10A2_UNORM: 913 case PIPE_FORMAT_B10G10R10A2_UINT: 914 return V_028C70_SWAP_ALT; 915 916 case PIPE_FORMAT_R11G11B10_FLOAT: 917 case PIPE_FORMAT_R32_FLOAT: 918 case PIPE_FORMAT_R32_UINT: 919 case PIPE_FORMAT_R32_SINT: 920 case PIPE_FORMAT_Z32_FLOAT: 921 case PIPE_FORMAT_R16G16_FLOAT: 922 case PIPE_FORMAT_R16G16_UNORM: 923 case PIPE_FORMAT_R16G16_UINT: 924 case PIPE_FORMAT_R16G16_SINT: 925 return V_028C70_SWAP_STD; 926 927 /* 64-bit buffers. */ 928 case PIPE_FORMAT_R32G32_FLOAT: 929 case PIPE_FORMAT_R32G32_UINT: 930 case PIPE_FORMAT_R32G32_SINT: 931 case PIPE_FORMAT_R16G16B16A16_UNORM: 932 case PIPE_FORMAT_R16G16B16A16_SNORM: 933 case PIPE_FORMAT_R16G16B16A16_USCALED: 934 case PIPE_FORMAT_R16G16B16A16_SSCALED: 935 case PIPE_FORMAT_R16G16B16A16_UINT: 936 case PIPE_FORMAT_R16G16B16A16_SINT: 937 case PIPE_FORMAT_R16G16B16A16_FLOAT: 938 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 939 940 /* 128-bit buffers. */ 941 case PIPE_FORMAT_R32G32B32A32_FLOAT: 942 case PIPE_FORMAT_R32G32B32A32_SNORM: 943 case PIPE_FORMAT_R32G32B32A32_UNORM: 944 case PIPE_FORMAT_R32G32B32A32_SSCALED: 945 case PIPE_FORMAT_R32G32B32A32_USCALED: 946 case PIPE_FORMAT_R32G32B32A32_SINT: 947 case PIPE_FORMAT_R32G32B32A32_UINT: 948 return V_028C70_SWAP_STD; 949 default: 950 R600_ERR("unsupported colorswap format %d\n", format); 951 return ~0U; 952 } 953 return ~0U; 954 } 955 956 static uint32_t si_colorformat_endian_swap(uint32_t colorformat) 957 { 958 if (R600_BIG_ENDIAN) { 959 switch(colorformat) { 960 /* 8-bit buffers. */ 961 case V_028C70_COLOR_8: 962 return V_028C70_ENDIAN_NONE; 963 964 /* 16-bit buffers. */ 965 case V_028C70_COLOR_5_6_5: 966 case V_028C70_COLOR_1_5_5_5: 967 case V_028C70_COLOR_4_4_4_4: 968 case V_028C70_COLOR_16: 969 case V_028C70_COLOR_8_8: 970 return V_028C70_ENDIAN_8IN16; 971 972 /* 32-bit buffers. */ 973 case V_028C70_COLOR_8_8_8_8: 974 case V_028C70_COLOR_2_10_10_10: 975 case V_028C70_COLOR_8_24: 976 case V_028C70_COLOR_24_8: 977 case V_028C70_COLOR_16_16: 978 return V_028C70_ENDIAN_8IN32; 979 980 /* 64-bit buffers. */ 981 case V_028C70_COLOR_16_16_16_16: 982 return V_028C70_ENDIAN_8IN16; 983 984 case V_028C70_COLOR_32_32: 985 return V_028C70_ENDIAN_8IN32; 986 987 /* 128-bit buffers. */ 988 case V_028C70_COLOR_32_32_32_32: 989 return V_028C70_ENDIAN_8IN32; 990 default: 991 return V_028C70_ENDIAN_NONE; /* Unsupported. */ 992 } 993 } else { 994 return V_028C70_ENDIAN_NONE; 995 } 996 } 997 998 /* Returns the size in bits of the widest component of a CB format */ 999 static unsigned si_colorformat_max_comp_size(uint32_t colorformat) 1000 { 1001 switch(colorformat) { 1002 case V_028C70_COLOR_4_4_4_4: 1003 return 4; 1004 1005 case V_028C70_COLOR_1_5_5_5: 1006 case V_028C70_COLOR_5_5_5_1: 1007 return 5; 1008 1009 case V_028C70_COLOR_5_6_5: 1010 return 6; 1011 1012 case V_028C70_COLOR_8: 1013 case V_028C70_COLOR_8_8: 1014 case V_028C70_COLOR_8_8_8_8: 1015 return 8; 1016 1017 case V_028C70_COLOR_10_10_10_2: 1018 case V_028C70_COLOR_2_10_10_10: 1019 return 10; 1020 1021 case V_028C70_COLOR_10_11_11: 1022 case V_028C70_COLOR_11_11_10: 1023 return 11; 1024 1025 case V_028C70_COLOR_16: 1026 case V_028C70_COLOR_16_16: 1027 case V_028C70_COLOR_16_16_16_16: 1028 return 16; 1029 1030 case V_028C70_COLOR_8_24: 1031 case V_028C70_COLOR_24_8: 1032 return 24; 1033 1034 case V_028C70_COLOR_32: 1035 case V_028C70_COLOR_32_32: 1036 case V_028C70_COLOR_32_32_32_32: 1037 case V_028C70_COLOR_X24_8_32_FLOAT: 1038 return 32; 1039 } 1040 1041 assert(!"Unknown maximum component size"); 1042 return 0; 1043 } 1044 1045 static uint32_t si_translate_dbformat(enum pipe_format format) 1046 { 1047 switch (format) { 1048 case PIPE_FORMAT_Z16_UNORM: 1049 return V_028040_Z_16; 1050 case PIPE_FORMAT_Z24X8_UNORM: 1051 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1052 return V_028040_Z_24; /* XXX no longer supported on SI */ 1053 case PIPE_FORMAT_Z32_FLOAT: 1054 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1055 return V_028040_Z_32_FLOAT; 1056 default: 1057 return ~0U; 1058 } 1059 } 1060 1061 /* 1062 * Texture translation 1063 */ 1064 1065 static uint32_t si_translate_texformat(struct pipe_screen *screen, 1066 enum pipe_format format, 1067 const struct util_format_description *desc, 1068 int first_non_void) 1069 { 1070 boolean uniform = TRUE; 1071 int i; 1072 1073 /* Colorspace (return non-RGB formats directly). */ 1074 switch (desc->colorspace) { 1075 /* Depth stencil formats */ 1076 case UTIL_FORMAT_COLORSPACE_ZS: 1077 switch (format) { 1078 case PIPE_FORMAT_Z16_UNORM: 1079 return V_008F14_IMG_DATA_FORMAT_16; 1080 case PIPE_FORMAT_X24S8_UINT: 1081 case PIPE_FORMAT_Z24X8_UNORM: 1082 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1083 return V_008F14_IMG_DATA_FORMAT_24_8; 1084 case PIPE_FORMAT_S8X24_UINT: 1085 case PIPE_FORMAT_X8Z24_UNORM: 1086 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1087 return V_008F14_IMG_DATA_FORMAT_8_24; 1088 case PIPE_FORMAT_S8_UINT: 1089 return V_008F14_IMG_DATA_FORMAT_8; 1090 case PIPE_FORMAT_Z32_FLOAT: 1091 return V_008F14_IMG_DATA_FORMAT_32; 1092 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1093 return V_008F14_IMG_DATA_FORMAT_X24_8_32; 1094 default: 1095 goto out_unknown; 1096 } 1097 1098 case UTIL_FORMAT_COLORSPACE_YUV: 1099 goto out_unknown; /* TODO */ 1100 1101 case UTIL_FORMAT_COLORSPACE_SRGB: 1102 break; 1103 1104 default: 1105 break; 1106 } 1107 1108 /* TODO compressed formats */ 1109 1110 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 1111 return V_008F14_IMG_DATA_FORMAT_5_9_9_9; 1112 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 1113 return V_008F14_IMG_DATA_FORMAT_10_11_11; 1114 } 1115 1116 /* R8G8Bx_SNORM - TODO CxV8U8 */ 1117 1118 /* See whether the components are of the same size. */ 1119 for (i = 1; i < desc->nr_channels; i++) { 1120 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 1121 } 1122 1123 /* Non-uniform formats. */ 1124 if (!uniform) { 1125 switch(desc->nr_channels) { 1126 case 3: 1127 if (desc->channel[0].size == 5 && 1128 desc->channel[1].size == 6 && 1129 desc->channel[2].size == 5) { 1130 return V_008F14_IMG_DATA_FORMAT_5_6_5; 1131 } 1132 goto out_unknown; 1133 case 4: 1134 if (desc->channel[0].size == 5 && 1135 desc->channel[1].size == 5 && 1136 desc->channel[2].size == 5 && 1137 desc->channel[3].size == 1) { 1138 return V_008F14_IMG_DATA_FORMAT_1_5_5_5; 1139 } 1140 if (desc->channel[0].size == 10 && 1141 desc->channel[1].size == 10 && 1142 desc->channel[2].size == 10 && 1143 desc->channel[3].size == 2) { 1144 return V_008F14_IMG_DATA_FORMAT_2_10_10_10; 1145 } 1146 goto out_unknown; 1147 } 1148 goto out_unknown; 1149 } 1150 1151 if (first_non_void < 0 || first_non_void > 3) 1152 goto out_unknown; 1153 1154 /* uniform formats */ 1155 switch (desc->channel[first_non_void].size) { 1156 case 4: 1157 switch (desc->nr_channels) { 1158 case 2: 1159 return V_008F14_IMG_DATA_FORMAT_4_4; 1160 case 4: 1161 return V_008F14_IMG_DATA_FORMAT_4_4_4_4; 1162 } 1163 break; 1164 case 8: 1165 switch (desc->nr_channels) { 1166 case 1: 1167 return V_008F14_IMG_DATA_FORMAT_8; 1168 case 2: 1169 return V_008F14_IMG_DATA_FORMAT_8_8; 1170 case 4: 1171 return V_008F14_IMG_DATA_FORMAT_8_8_8_8; 1172 } 1173 break; 1174 case 16: 1175 switch (desc->nr_channels) { 1176 case 1: 1177 return V_008F14_IMG_DATA_FORMAT_16; 1178 case 2: 1179 return V_008F14_IMG_DATA_FORMAT_16_16; 1180 case 4: 1181 return V_008F14_IMG_DATA_FORMAT_16_16_16_16; 1182 } 1183 break; 1184 case 32: 1185 switch (desc->nr_channels) { 1186 case 1: 1187 return V_008F14_IMG_DATA_FORMAT_32; 1188 case 2: 1189 return V_008F14_IMG_DATA_FORMAT_32_32; 1190 case 3: 1191 return V_008F14_IMG_DATA_FORMAT_32_32_32; 1192 case 4: 1193 return V_008F14_IMG_DATA_FORMAT_32_32_32_32; 1194 } 1195 } 1196 1197 out_unknown: 1198 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1199 return ~0; 1200 } 1201 1202 static unsigned si_tex_wrap(unsigned wrap) 1203 { 1204 switch (wrap) { 1205 default: 1206 case PIPE_TEX_WRAP_REPEAT: 1207 return V_008F30_SQ_TEX_WRAP; 1208 case PIPE_TEX_WRAP_CLAMP: 1209 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER; 1210 case PIPE_TEX_WRAP_CLAMP_TO_EDGE: 1211 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL; 1212 case PIPE_TEX_WRAP_CLAMP_TO_BORDER: 1213 return V_008F30_SQ_TEX_CLAMP_BORDER; 1214 case PIPE_TEX_WRAP_MIRROR_REPEAT: 1215 return V_008F30_SQ_TEX_MIRROR; 1216 case PIPE_TEX_WRAP_MIRROR_CLAMP: 1217 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER; 1218 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: 1219 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL; 1220 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: 1221 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER; 1222 } 1223 } 1224 1225 static unsigned si_tex_filter(unsigned filter) 1226 { 1227 switch (filter) { 1228 default: 1229 case PIPE_TEX_FILTER_NEAREST: 1230 return V_008F38_SQ_TEX_XY_FILTER_POINT; 1231 case PIPE_TEX_FILTER_LINEAR: 1232 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR; 1233 } 1234 } 1235 1236 static unsigned si_tex_mipfilter(unsigned filter) 1237 { 1238 switch (filter) { 1239 case PIPE_TEX_MIPFILTER_NEAREST: 1240 return V_008F38_SQ_TEX_Z_FILTER_POINT; 1241 case PIPE_TEX_MIPFILTER_LINEAR: 1242 return V_008F38_SQ_TEX_Z_FILTER_LINEAR; 1243 default: 1244 case PIPE_TEX_MIPFILTER_NONE: 1245 return V_008F38_SQ_TEX_Z_FILTER_NONE; 1246 } 1247 } 1248 1249 static unsigned si_tex_compare(unsigned compare) 1250 { 1251 switch (compare) { 1252 default: 1253 case PIPE_FUNC_NEVER: 1254 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER; 1255 case PIPE_FUNC_LESS: 1256 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS; 1257 case PIPE_FUNC_EQUAL: 1258 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL; 1259 case PIPE_FUNC_LEQUAL: 1260 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL; 1261 case PIPE_FUNC_GREATER: 1262 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER; 1263 case PIPE_FUNC_NOTEQUAL: 1264 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL; 1265 case PIPE_FUNC_GEQUAL: 1266 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL; 1267 case PIPE_FUNC_ALWAYS: 1268 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS; 1269 } 1270 } 1271 1272 static unsigned si_tex_dim(unsigned dim) 1273 { 1274 switch (dim) { 1275 default: 1276 case PIPE_TEXTURE_1D: 1277 return V_008F1C_SQ_RSRC_IMG_1D; 1278 case PIPE_TEXTURE_1D_ARRAY: 1279 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY; 1280 case PIPE_TEXTURE_2D: 1281 case PIPE_TEXTURE_RECT: 1282 return V_008F1C_SQ_RSRC_IMG_2D; 1283 case PIPE_TEXTURE_2D_ARRAY: 1284 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY; 1285 case PIPE_TEXTURE_3D: 1286 return V_008F1C_SQ_RSRC_IMG_3D; 1287 case PIPE_TEXTURE_CUBE: 1288 return V_008F1C_SQ_RSRC_IMG_CUBE; 1289 } 1290 } 1291 1292 /* 1293 * Format support testing 1294 */ 1295 1296 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) 1297 { 1298 return si_translate_texformat(screen, format, util_format_description(format), 1299 util_format_get_first_non_void_channel(format)) != ~0U; 1300 } 1301 1302 static uint32_t si_translate_vertexformat(struct pipe_screen *screen, 1303 enum pipe_format format, 1304 const struct util_format_description *desc, 1305 int first_non_void) 1306 { 1307 unsigned type = desc->channel[first_non_void].type; 1308 int i; 1309 1310 if (type == UTIL_FORMAT_TYPE_FIXED) 1311 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1312 1313 /* See whether the components are of the same size. */ 1314 for (i = 0; i < desc->nr_channels; i++) { 1315 if (desc->channel[first_non_void].size != desc->channel[i].size) 1316 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1317 } 1318 1319 switch (desc->channel[first_non_void].size) { 1320 case 8: 1321 switch (desc->nr_channels) { 1322 case 1: 1323 return V_008F0C_BUF_DATA_FORMAT_8; 1324 case 2: 1325 return V_008F0C_BUF_DATA_FORMAT_8_8; 1326 case 3: 1327 case 4: 1328 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8; 1329 } 1330 break; 1331 case 16: 1332 switch (desc->nr_channels) { 1333 case 1: 1334 return V_008F0C_BUF_DATA_FORMAT_16; 1335 case 2: 1336 return V_008F0C_BUF_DATA_FORMAT_16_16; 1337 case 3: 1338 case 4: 1339 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16; 1340 } 1341 break; 1342 case 32: 1343 if (type != UTIL_FORMAT_TYPE_FLOAT) 1344 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1345 1346 switch (desc->nr_channels) { 1347 case 1: 1348 return V_008F0C_BUF_DATA_FORMAT_32; 1349 case 2: 1350 return V_008F0C_BUF_DATA_FORMAT_32_32; 1351 case 3: 1352 return V_008F0C_BUF_DATA_FORMAT_32_32_32; 1353 case 4: 1354 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32; 1355 } 1356 break; 1357 } 1358 1359 return V_008F0C_BUF_DATA_FORMAT_INVALID; 1360 } 1361 1362 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format) 1363 { 1364 const struct util_format_description *desc; 1365 int first_non_void; 1366 unsigned data_format; 1367 1368 desc = util_format_description(format); 1369 first_non_void = util_format_get_first_non_void_channel(format); 1370 data_format = si_translate_vertexformat(screen, format, desc, first_non_void); 1371 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID; 1372 } 1373 1374 static bool si_is_colorbuffer_format_supported(enum pipe_format format) 1375 { 1376 return si_translate_colorformat(format) != ~0U && 1377 si_translate_colorswap(format) != ~0U; 1378 } 1379 1380 static bool si_is_zs_format_supported(enum pipe_format format) 1381 { 1382 return si_translate_dbformat(format) != ~0U; 1383 } 1384 1385 bool si_is_format_supported(struct pipe_screen *screen, 1386 enum pipe_format format, 1387 enum pipe_texture_target target, 1388 unsigned sample_count, 1389 unsigned usage) 1390 { 1391 unsigned retval = 0; 1392 1393 if (target >= PIPE_MAX_TEXTURE_TYPES) { 1394 R600_ERR("r600: unsupported texture type %d\n", target); 1395 return FALSE; 1396 } 1397 1398 if (!util_format_is_supported(format, usage)) 1399 return FALSE; 1400 1401 /* Multisample */ 1402 if (sample_count > 1) 1403 return FALSE; 1404 1405 if ((usage & PIPE_BIND_SAMPLER_VIEW) && 1406 si_is_sampler_format_supported(screen, format)) { 1407 retval |= PIPE_BIND_SAMPLER_VIEW; 1408 } 1409 1410 if ((usage & (PIPE_BIND_RENDER_TARGET | 1411 PIPE_BIND_DISPLAY_TARGET | 1412 PIPE_BIND_SCANOUT | 1413 PIPE_BIND_SHARED)) && 1414 si_is_colorbuffer_format_supported(format)) { 1415 retval |= usage & 1416 (PIPE_BIND_RENDER_TARGET | 1417 PIPE_BIND_DISPLAY_TARGET | 1418 PIPE_BIND_SCANOUT | 1419 PIPE_BIND_SHARED); 1420 } 1421 1422 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 1423 si_is_zs_format_supported(format)) { 1424 retval |= PIPE_BIND_DEPTH_STENCIL; 1425 } 1426 1427 if ((usage & PIPE_BIND_VERTEX_BUFFER) && 1428 si_is_vertex_format_supported(screen, format)) { 1429 retval |= PIPE_BIND_VERTEX_BUFFER; 1430 } 1431 1432 if (usage & PIPE_BIND_TRANSFER_READ) 1433 retval |= PIPE_BIND_TRANSFER_READ; 1434 if (usage & PIPE_BIND_TRANSFER_WRITE) 1435 retval |= PIPE_BIND_TRANSFER_WRITE; 1436 1437 return retval == usage; 1438 } 1439 1440 /* 1441 * framebuffer handling 1442 */ 1443 1444 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4, 1445 const struct pipe_framebuffer_state *state, int cb) 1446 { 1447 struct r600_resource_texture *rtex; 1448 struct r600_surface *surf; 1449 unsigned level = state->cbufs[cb]->u.tex.level; 1450 unsigned pitch, slice; 1451 unsigned color_info, color_attrib; 1452 unsigned format, swap, ntype, endian; 1453 uint64_t offset; 1454 unsigned blocksize; 1455 const struct util_format_description *desc; 1456 int i; 1457 unsigned blend_clamp = 0, blend_bypass = 0; 1458 unsigned max_comp_size; 1459 1460 surf = (struct r600_surface *)state->cbufs[cb]; 1461 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; 1462 blocksize = util_format_get_blocksize(rtex->real_format); 1463 1464 if (rtex->depth) 1465 rctx->have_depth_fb = TRUE; 1466 1467 if (rtex->depth && !rtex->is_flushing_texture) { 1468 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE); 1469 rtex = rtex->flushed_depth_texture; 1470 } 1471 1472 offset = rtex->surface.level[level].offset; 1473 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1474 offset += rtex->surface.level[level].slice_size * 1475 state->cbufs[cb]->u.tex.first_layer; 1476 } 1477 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1; 1478 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1479 if (slice) { 1480 slice = slice - 1; 1481 } 1482 1483 color_attrib = S_028C74_TILE_MODE_INDEX(8); 1484 switch (rtex->surface.level[level].mode) { 1485 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1486 color_attrib = S_028C74_TILE_MODE_INDEX(8); 1487 break; 1488 case RADEON_SURF_MODE_1D: 1489 color_attrib = S_028C74_TILE_MODE_INDEX(9); 1490 break; 1491 case RADEON_SURF_MODE_2D: 1492 if (rtex->resource.b.b.bind & PIPE_BIND_SCANOUT) { 1493 switch (blocksize) { 1494 case 1: 1495 color_attrib = S_028C74_TILE_MODE_INDEX(10); 1496 break; 1497 case 2: 1498 color_attrib = S_028C74_TILE_MODE_INDEX(11); 1499 break; 1500 case 4: 1501 color_attrib = S_028C74_TILE_MODE_INDEX(12); 1502 break; 1503 } 1504 break; 1505 } else switch (blocksize) { 1506 case 1: 1507 color_attrib = S_028C74_TILE_MODE_INDEX(14); 1508 break; 1509 case 2: 1510 color_attrib = S_028C74_TILE_MODE_INDEX(15); 1511 break; 1512 case 4: 1513 color_attrib = S_028C74_TILE_MODE_INDEX(16); 1514 break; 1515 case 8: 1516 color_attrib = S_028C74_TILE_MODE_INDEX(17); 1517 break; 1518 default: 1519 color_attrib = S_028C74_TILE_MODE_INDEX(13); 1520 } 1521 break; 1522 } 1523 1524 desc = util_format_description(surf->base.format); 1525 for (i = 0; i < 4; i++) { 1526 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1527 break; 1528 } 1529 } 1530 if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) { 1531 ntype = V_028C70_NUMBER_FLOAT; 1532 } else { 1533 ntype = V_028C70_NUMBER_UNORM; 1534 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 1535 ntype = V_028C70_NUMBER_SRGB; 1536 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1537 if (desc->channel[i].normalized) 1538 ntype = V_028C70_NUMBER_SNORM; 1539 else if (desc->channel[i].pure_integer) 1540 ntype = V_028C70_NUMBER_SINT; 1541 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { 1542 if (desc->channel[i].normalized) 1543 ntype = V_028C70_NUMBER_UNORM; 1544 else if (desc->channel[i].pure_integer) 1545 ntype = V_028C70_NUMBER_UINT; 1546 } 1547 } 1548 1549 format = si_translate_colorformat(surf->base.format); 1550 swap = si_translate_colorswap(surf->base.format); 1551 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) { 1552 endian = V_028C70_ENDIAN_NONE; 1553 } else { 1554 endian = si_colorformat_endian_swap(format); 1555 } 1556 1557 /* blend clamp should be set for all NORM/SRGB types */ 1558 if (ntype == V_028C70_NUMBER_UNORM || 1559 ntype == V_028C70_NUMBER_SNORM || 1560 ntype == V_028C70_NUMBER_SRGB) 1561 blend_clamp = 1; 1562 1563 /* set blend bypass according to docs if SINT/UINT or 1564 8/24 COLOR variants */ 1565 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT || 1566 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 || 1567 format == V_028C70_COLOR_X24_8_32_FLOAT) { 1568 blend_clamp = 0; 1569 blend_bypass = 1; 1570 } 1571 1572 color_info = S_028C70_FORMAT(format) | 1573 S_028C70_COMP_SWAP(swap) | 1574 S_028C70_BLEND_CLAMP(blend_clamp) | 1575 S_028C70_BLEND_BYPASS(blend_bypass) | 1576 S_028C70_NUMBER_TYPE(ntype) | 1577 S_028C70_ENDIAN(endian); 1578 1579 rctx->alpha_ref_dirty = true; 1580 1581 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture); 1582 offset >>= 8; 1583 1584 /* FIXME handle enabling of CB beyond BASE8 which has different offset */ 1585 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE); 1586 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset); 1587 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch)); 1588 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice)); 1589 1590 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1591 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000); 1592 } else { 1593 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 1594 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) | 1595 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer)); 1596 } 1597 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info); 1598 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib); 1599 1600 /* Determine pixel shader export format */ 1601 max_comp_size = si_colorformat_max_comp_size(format); 1602 if (ntype == V_028C70_NUMBER_SRGB || 1603 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) && 1604 max_comp_size <= 10) || 1605 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) { 1606 rctx->export_16bpc |= 1 << cb; 1607 rctx->spi_shader_col_format |= V_028714_SPI_SHADER_FP16_ABGR << (4 * cb); 1608 } else 1609 rctx->spi_shader_col_format |= V_028714_SPI_SHADER_32_ABGR << (4 * cb); 1610 } 1611 1612 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4, 1613 const struct pipe_framebuffer_state *state) 1614 { 1615 struct r600_resource_texture *rtex; 1616 struct r600_surface *surf; 1617 unsigned level, pitch, slice, format; 1618 uint32_t z_info, s_info; 1619 uint64_t z_offs, s_offs; 1620 1621 if (state->zsbuf == NULL) { 1622 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0); 1623 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0); 1624 return; 1625 } 1626 1627 surf = (struct r600_surface *)state->zsbuf; 1628 level = surf->base.u.tex.level; 1629 rtex = (struct r600_resource_texture*)surf->base.texture; 1630 1631 format = si_translate_dbformat(rtex->real_format); 1632 1633 z_offs = r600_resource_va(rctx->context.screen, surf->base.texture); 1634 z_offs += rtex->surface.level[level].offset; 1635 1636 s_offs = r600_resource_va(rctx->context.screen, surf->base.texture); 1637 s_offs += rtex->surface.stencil_offset; 1638 z_offs += rtex->surface.level[level].offset / 4; 1639 1640 z_offs >>= 8; 1641 s_offs >>= 8; 1642 1643 pitch = (rtex->surface.level[level].nblk_x / 8) - 1; 1644 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1645 if (slice) { 1646 slice = slice - 1; 1647 } 1648 1649 z_info = S_028040_FORMAT(format); 1650 s_info = S_028044_FORMAT(1); 1651 1652 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_1D) { 1653 z_info |= S_028040_TILE_MODE_INDEX(4); 1654 s_info |= S_028044_TILE_MODE_INDEX(4); 1655 1656 } else if (rtex->surface.level[level].mode == RADEON_SURF_MODE_2D) { 1657 switch (format) { 1658 case V_028040_Z_16: 1659 z_info |= S_028040_TILE_MODE_INDEX(5); 1660 s_info |= S_028044_TILE_MODE_INDEX(5); 1661 break; 1662 case V_028040_Z_24: 1663 case V_028040_Z_32_FLOAT: 1664 z_info |= S_028040_TILE_MODE_INDEX(6); 1665 s_info |= S_028044_TILE_MODE_INDEX(6); 1666 break; 1667 default: 1668 z_info |= S_028040_TILE_MODE_INDEX(7); 1669 s_info |= S_028044_TILE_MODE_INDEX(7); 1670 } 1671 1672 } else { 1673 R600_ERR("Invalid DB tiling mode %d!\n", 1674 rtex->surface.level[level].mode); 1675 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0); 1676 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0); 1677 return; 1678 } 1679 1680 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW, 1681 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) | 1682 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer)); 1683 1684 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1); 1685 if (format != ~0U) { 1686 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info); 1687 1688 } else { 1689 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0); 1690 } 1691 1692 if (rtex->surface.flags & RADEON_SURF_SBUFFER) { 1693 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info); 1694 } else { 1695 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0); 1696 } 1697 1698 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE); 1699 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs); 1700 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs); 1701 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs); 1702 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs); 1703 1704 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch)); 1705 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice)); 1706 } 1707 1708 static void si_set_framebuffer_state(struct pipe_context *ctx, 1709 const struct pipe_framebuffer_state *state) 1710 { 1711 struct r600_context *rctx = (struct r600_context *)ctx; 1712 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 1713 uint32_t shader_mask, tl, br; 1714 int tl_x, tl_y, br_x, br_y; 1715 1716 if (pm4 == NULL) 1717 return; 1718 1719 si_pm4_inval_fb_cache(pm4, state->nr_cbufs); 1720 1721 if (state->zsbuf) 1722 si_pm4_inval_zsbuf_cache(pm4); 1723 1724 util_copy_framebuffer_state(&rctx->framebuffer, state); 1725 1726 /* build states */ 1727 rctx->have_depth_fb = 0; 1728 rctx->export_16bpc = 0; 1729 rctx->spi_shader_col_format = 0; 1730 for (int i = 0; i < state->nr_cbufs; i++) { 1731 si_cb(rctx, pm4, state, i); 1732 } 1733 assert(!(rctx->export_16bpc & ~0xff)); 1734 si_db(rctx, pm4, state); 1735 1736 shader_mask = 0; 1737 for (int i = 0; i < state->nr_cbufs; i++) { 1738 shader_mask |= 0xf << (i * 4); 1739 } 1740 tl_x = 0; 1741 tl_y = 0; 1742 br_x = state->width; 1743 br_y = state->height; 1744 #if 0 /* These shouldn't be necessary on SI, see PA_SC_ENHANCE register */ 1745 /* EG hw workaround */ 1746 if (br_x == 0) 1747 tl_x = 1; 1748 if (br_y == 0) 1749 tl_y = 1; 1750 /* cayman hw workaround */ 1751 if (rctx->chip_class == CAYMAN) { 1752 if (br_x == 1 && br_y == 1) 1753 br_x = 2; 1754 } 1755 #endif 1756 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y); 1757 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y); 1758 1759 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl); 1760 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br); 1761 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl); 1762 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br); 1763 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl); 1764 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br); 1765 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl); 1766 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br); 1767 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000); 1768 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); 1769 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask); 1770 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, 1771 rctx->spi_shader_col_format); 1772 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000); 1773 1774 si_pm4_set_state(rctx, framebuffer, pm4); 1775 si_update_fb_rs_state(rctx); 1776 si_update_fb_blend_state(rctx); 1777 } 1778 1779 /* 1780 * shaders 1781 */ 1782 1783 /* Compute the key for the hw shader variant */ 1784 static INLINE unsigned si_shader_selector_key(struct pipe_context *ctx, 1785 struct si_pipe_shader_selector *sel) 1786 { 1787 struct r600_context *rctx = (struct r600_context *)ctx; 1788 unsigned key = 0; 1789 1790 if (sel->type == PIPE_SHADER_FRAGMENT) { 1791 if (sel->fs_write_all) 1792 key |= rctx->framebuffer.nr_cbufs; 1793 key |= rctx->export_16bpc << 4; 1794 /*if (rctx->queued.named.rasterizer) 1795 key |= rctx->queued.named.rasterizer->flatshade << 12;*/ 1796 /*key |== rctx->two_side << 13;*/ 1797 } 1798 1799 return key; 1800 } 1801 1802 /* Select the hw shader variant depending on the current state. 1803 * (*dirty) is set to 1 if current variant was changed */ 1804 int si_shader_select(struct pipe_context *ctx, 1805 struct si_pipe_shader_selector *sel, 1806 unsigned *dirty) 1807 { 1808 unsigned key; 1809 struct si_pipe_shader * shader = NULL; 1810 int r; 1811 1812 key = si_shader_selector_key(ctx, sel); 1813 1814 /* Check if we don't need to change anything. 1815 * This path is also used for most shaders that don't need multiple 1816 * variants, it will cost just a computation of the key and this 1817 * test. */ 1818 if (likely(sel->current && sel->current->key == key)) { 1819 return 0; 1820 } 1821 1822 /* lookup if we have other variants in the list */ 1823 if (sel->num_shaders > 1) { 1824 struct si_pipe_shader *p = sel->current, *c = p->next_variant; 1825 1826 while (c && c->key != key) { 1827 p = c; 1828 c = c->next_variant; 1829 } 1830 1831 if (c) { 1832 p->next_variant = c->next_variant; 1833 shader = c; 1834 } 1835 } 1836 1837 if (unlikely(!shader)) { 1838 shader = CALLOC(1, sizeof(struct si_pipe_shader)); 1839 shader->selector = sel; 1840 1841 r = si_pipe_shader_create(ctx, shader); 1842 if (unlikely(r)) { 1843 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n", 1844 sel->type, key, r); 1845 sel->current = NULL; 1846 return r; 1847 } 1848 1849 /* We don't know the value of fs_write_all property until we built 1850 * at least one variant, so we may need to recompute the key (include 1851 * rctx->framebuffer.nr_cbufs) after building first variant. */ 1852 if (sel->type == PIPE_SHADER_FRAGMENT && 1853 sel->num_shaders == 0 && 1854 shader->shader.fs_write_all) { 1855 sel->fs_write_all = 1; 1856 key = si_shader_selector_key(ctx, sel); 1857 } 1858 1859 shader->key = key; 1860 sel->num_shaders++; 1861 } 1862 1863 if (dirty) 1864 *dirty = 1; 1865 1866 shader->next_variant = sel->current; 1867 sel->current = shader; 1868 1869 return 0; 1870 } 1871 1872 static void *si_create_shader_state(struct pipe_context *ctx, 1873 const struct pipe_shader_state *state, 1874 unsigned pipe_shader_type) 1875 { 1876 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector); 1877 int r; 1878 1879 sel->type = pipe_shader_type; 1880 sel->tokens = tgsi_dup_tokens(state->tokens); 1881 sel->so = state->stream_output; 1882 1883 r = si_shader_select(ctx, sel, NULL); 1884 if (r) { 1885 free(sel); 1886 return NULL; 1887 } 1888 1889 return sel; 1890 } 1891 1892 static void *si_create_fs_state(struct pipe_context *ctx, 1893 const struct pipe_shader_state *state) 1894 { 1895 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT); 1896 } 1897 1898 static void *si_create_vs_state(struct pipe_context *ctx, 1899 const struct pipe_shader_state *state) 1900 { 1901 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX); 1902 } 1903 1904 static void si_bind_vs_shader(struct pipe_context *ctx, void *state) 1905 { 1906 struct r600_context *rctx = (struct r600_context *)ctx; 1907 struct si_pipe_shader_selector *sel = state; 1908 1909 if (rctx->vs_shader == sel) 1910 return; 1911 1912 rctx->shader_dirty = true; 1913 rctx->vs_shader = sel; 1914 1915 if (sel && sel->current) 1916 si_pm4_bind_state(rctx, vs, sel->current->pm4); 1917 else 1918 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4); 1919 } 1920 1921 static void si_bind_ps_shader(struct pipe_context *ctx, void *state) 1922 { 1923 struct r600_context *rctx = (struct r600_context *)ctx; 1924 struct si_pipe_shader_selector *sel = state; 1925 1926 if (rctx->ps_shader == sel) 1927 return; 1928 1929 rctx->shader_dirty = true; 1930 rctx->ps_shader = sel; 1931 1932 if (sel && sel->current) 1933 si_pm4_bind_state(rctx, ps, sel->current->pm4); 1934 else 1935 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4); 1936 } 1937 1938 static void si_delete_shader_selector(struct pipe_context *ctx, 1939 struct si_pipe_shader_selector *sel) 1940 { 1941 struct r600_context *rctx = (struct r600_context *)ctx; 1942 struct si_pipe_shader *p = sel->current, *c; 1943 1944 while (p) { 1945 c = p->next_variant; 1946 si_pm4_delete_state(rctx, vs, p->pm4); 1947 si_pipe_shader_destroy(ctx, p); 1948 free(p); 1949 p = c; 1950 } 1951 1952 free(sel->tokens); 1953 free(sel); 1954 } 1955 1956 static void si_delete_vs_shader(struct pipe_context *ctx, void *state) 1957 { 1958 struct r600_context *rctx = (struct r600_context *)ctx; 1959 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state; 1960 1961 if (rctx->vs_shader == sel) { 1962 rctx->vs_shader = NULL; 1963 } 1964 1965 si_delete_shader_selector(ctx, sel); 1966 } 1967 1968 static void si_delete_ps_shader(struct pipe_context *ctx, void *state) 1969 { 1970 struct r600_context *rctx = (struct r600_context *)ctx; 1971 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state; 1972 1973 if (rctx->ps_shader == sel) { 1974 rctx->ps_shader = NULL; 1975 } 1976 1977 si_delete_shader_selector(ctx, sel); 1978 } 1979 1980 /* 1981 * Samplers 1982 */ 1983 1984 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx, 1985 struct pipe_resource *texture, 1986 const struct pipe_sampler_view *state) 1987 { 1988 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view); 1989 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture; 1990 const struct util_format_description *desc = util_format_description(state->format); 1991 unsigned blocksize = util_format_get_blocksize(tmp->real_format); 1992 unsigned format, num_format, /*endian,*/ tiling_index; 1993 uint32_t pitch = 0; 1994 unsigned char state_swizzle[4], swizzle[4]; 1995 unsigned height, depth, width, offset_level, last_level; 1996 int first_non_void; 1997 uint64_t va; 1998 1999 if (view == NULL) 2000 return NULL; 2001 2002 /* initialize base object */ 2003 view->base = *state; 2004 view->base.texture = NULL; 2005 pipe_reference(NULL, &texture->reference); 2006 view->base.texture = texture; 2007 view->base.reference.count = 1; 2008 view->base.context = ctx; 2009 2010 state_swizzle[0] = state->swizzle_r; 2011 state_swizzle[1] = state->swizzle_g; 2012 state_swizzle[2] = state->swizzle_b; 2013 state_swizzle[3] = state->swizzle_a; 2014 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle); 2015 2016 first_non_void = util_format_get_first_non_void_channel(state->format); 2017 switch (desc->channel[first_non_void].type) { 2018 case UTIL_FORMAT_TYPE_FLOAT: 2019 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; 2020 break; 2021 case UTIL_FORMAT_TYPE_SIGNED: 2022 num_format = V_008F14_IMG_NUM_FORMAT_SNORM; 2023 break; 2024 case UTIL_FORMAT_TYPE_UNSIGNED: 2025 default: 2026 num_format = V_008F14_IMG_NUM_FORMAT_UNORM; 2027 } 2028 2029 format = si_translate_texformat(ctx->screen, state->format, desc, first_non_void); 2030 if (format == ~0) { 2031 format = 0; 2032 } 2033 2034 if (tmp->depth && !tmp->is_flushing_texture) { 2035 r600_texture_depth_flush(ctx, texture, TRUE); 2036 tmp = tmp->flushed_depth_texture; 2037 } 2038 2039 /* not supported any more */ 2040 //endian = si_colorformat_endian_swap(format); 2041 2042 offset_level = state->u.tex.first_level; 2043 last_level = state->u.tex.last_level - offset_level; 2044 width = tmp->surface.level[offset_level].npix_x; 2045 height = tmp->surface.level[offset_level].npix_y; 2046 depth = tmp->surface.level[offset_level].npix_z; 2047 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format); 2048 2049 if (texture->target == PIPE_TEXTURE_1D_ARRAY) { 2050 height = 1; 2051 depth = texture->array_size; 2052 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { 2053 depth = texture->array_size; 2054 } 2055 2056 tiling_index = 8; 2057 switch (tmp->surface.level[state->u.tex.first_level].mode) { 2058 case RADEON_SURF_MODE_LINEAR_ALIGNED: 2059 tiling_index = 8; 2060 break; 2061 case RADEON_SURF_MODE_1D: 2062 tiling_index = 9; 2063 break; 2064 case RADEON_SURF_MODE_2D: 2065 if (tmp->resource.b.b.bind & PIPE_BIND_SCANOUT) { 2066 switch (blocksize) { 2067 case 1: 2068 tiling_index = 10; 2069 break; 2070 case 2: 2071 tiling_index = 11; 2072 break; 2073 case 4: 2074 tiling_index = 12; 2075 break; 2076 } 2077 break; 2078 } else switch (blocksize) { 2079 case 1: 2080 tiling_index = 14; 2081 break; 2082 case 2: 2083 tiling_index = 15; 2084 break; 2085 case 4: 2086 tiling_index = 16; 2087 break; 2088 case 8: 2089 tiling_index = 17; 2090 break; 2091 default: 2092 tiling_index = 13; 2093 } 2094 break; 2095 } 2096 2097 va = r600_resource_va(ctx->screen, texture); 2098 va += tmp->surface.level[offset_level].offset; 2099 view->state[0] = va >> 8; 2100 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) | 2101 S_008F14_DATA_FORMAT(format) | 2102 S_008F14_NUM_FORMAT(num_format)); 2103 view->state[2] = (S_008F18_WIDTH(width - 1) | 2104 S_008F18_HEIGHT(height - 1)); 2105 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) | 2106 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) | 2107 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) | 2108 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) | 2109 S_008F1C_BASE_LEVEL(offset_level) | 2110 S_008F1C_LAST_LEVEL(last_level) | 2111 S_008F1C_TILING_INDEX(tiling_index) | 2112 S_008F1C_TYPE(si_tex_dim(texture->target))); 2113 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1)); 2114 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) | 2115 S_008F24_LAST_ARRAY(state->u.tex.last_layer)); 2116 view->state[6] = 0; 2117 view->state[7] = 0; 2118 2119 return &view->base; 2120 } 2121 2122 static void si_sampler_view_destroy(struct pipe_context *ctx, 2123 struct pipe_sampler_view *state) 2124 { 2125 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state; 2126 2127 pipe_resource_reference(&state->texture, NULL); 2128 FREE(resource); 2129 } 2130 2131 static void *si_create_sampler_state(struct pipe_context *ctx, 2132 const struct pipe_sampler_state *state) 2133 { 2134 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state); 2135 union util_color uc; 2136 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0; 2137 unsigned border_color_type; 2138 2139 if (rstate == NULL) { 2140 return NULL; 2141 } 2142 2143 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 2144 switch (uc.ui) { 2145 case 0x000000FF: 2146 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK; 2147 break; 2148 case 0x00000000: 2149 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; 2150 break; 2151 case 0xFFFFFFFF: 2152 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE; 2153 break; 2154 default: /* Use border color pointer */ 2155 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER; 2156 } 2157 2158 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) | 2159 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) | 2160 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) | 2161 (state->max_anisotropy & 0x7) << 9 | /* XXX */ 2162 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) | 2163 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) | 2164 aniso_flag_offset << 16 | /* XXX */ 2165 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map)); 2166 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) | 2167 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8))); 2168 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) | 2169 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) | 2170 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) | 2171 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter))); 2172 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type); 2173 2174 #if 0 2175 if (border_color_type == 3) { 2176 si_pm4_set_reg(pm4, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0])); 2177 si_pm4_set_reg(pm4, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1])); 2178 si_pm4_set_reg(pm4, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2])); 2179 si_pm4_set_reg(pm4, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3])); 2180 } 2181 #endif 2182 return rstate; 2183 } 2184 2185 static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count, 2186 struct pipe_sampler_view **views) 2187 { 2188 assert(count == 0); 2189 } 2190 2191 static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count, 2192 struct pipe_sampler_view **views) 2193 { 2194 struct r600_context *rctx = (struct r600_context *)ctx; 2195 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views; 2196 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 2197 int i, j; 2198 int has_depth = 0; 2199 2200 if (!count) 2201 goto out; 2202 2203 si_pm4_inval_texture_cache(pm4); 2204 2205 si_pm4_sh_data_begin(pm4); 2206 for (i = 0; i < count; i++) { 2207 pipe_sampler_view_reference( 2208 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i], 2209 views[i]); 2210 2211 if (views[i]) { 2212 struct r600_resource_texture *tex = (void *)resource[i]->base.texture; 2213 2214 si_pm4_add_bo(pm4, &tex->resource, RADEON_USAGE_READ); 2215 2216 for (j = 0; j < Elements(resource[i]->state); ++j) { 2217 si_pm4_sh_data_add(pm4, resource[i]->state[j]); 2218 } 2219 } 2220 } 2221 2222 for (i = count; i < NUM_TEX_UNITS; i++) { 2223 if (rctx->ps_samplers.views[i]) 2224 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL); 2225 } 2226 2227 si_pm4_sh_data_end(pm4, R_00B040_SPI_SHADER_USER_DATA_PS_4); 2228 2229 out: 2230 si_pm4_set_state(rctx, ps_sampler_views, pm4); 2231 rctx->have_depth_texture = has_depth; 2232 rctx->ps_samplers.n_views = count; 2233 } 2234 2235 static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states) 2236 { 2237 assert(count == 0); 2238 } 2239 2240 static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states) 2241 { 2242 struct r600_context *rctx = (struct r600_context *)ctx; 2243 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states; 2244 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 2245 int i, j; 2246 2247 if (!count) 2248 goto out; 2249 2250 si_pm4_inval_texture_cache(pm4); 2251 2252 si_pm4_sh_data_begin(pm4); 2253 for (i = 0; i < count; i++) { 2254 for (j = 0; j < Elements(rstates[i]->val); ++j) { 2255 si_pm4_sh_data_add(pm4, rstates[i]->val[j]); 2256 } 2257 } 2258 si_pm4_sh_data_end(pm4, R_00B038_SPI_SHADER_USER_DATA_PS_2); 2259 2260 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count); 2261 2262 out: 2263 si_pm4_set_state(rctx, ps_sampler, pm4); 2264 rctx->ps_samplers.n_samplers = count; 2265 } 2266 2267 static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 2268 { 2269 } 2270 2271 static void si_delete_sampler_state(struct pipe_context *ctx, void *state) 2272 { 2273 free(state); 2274 } 2275 2276 /* 2277 * Constants 2278 */ 2279 static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 2280 struct pipe_constant_buffer *cb) 2281 { 2282 struct r600_context *rctx = (struct r600_context *)ctx; 2283 struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL; 2284 struct si_pm4_state *pm4; 2285 uint64_t va_offset; 2286 uint32_t offset; 2287 2288 /* Note that the state tracker can unbind constant buffers by 2289 * passing NULL here. 2290 */ 2291 if (cb == NULL) 2292 return; 2293 2294 pm4 = CALLOC_STRUCT(si_pm4_state); 2295 si_pm4_inval_shader_cache(pm4); 2296 2297 if (cb->user_buffer) 2298 r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset); 2299 else 2300 offset = 0; 2301 va_offset = r600_resource_va(ctx->screen, (void*)rbuffer); 2302 va_offset += offset; 2303 2304 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ); 2305 2306 switch (shader) { 2307 case PIPE_SHADER_VERTEX: 2308 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, va_offset); 2309 si_pm4_set_reg(pm4, R_00B134_SPI_SHADER_USER_DATA_VS_1, va_offset >> 32); 2310 si_pm4_set_state(rctx, vs_const, pm4); 2311 break; 2312 2313 case PIPE_SHADER_FRAGMENT: 2314 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, va_offset); 2315 si_pm4_set_reg(pm4, R_00B034_SPI_SHADER_USER_DATA_PS_1, va_offset >> 32); 2316 si_pm4_set_state(rctx, ps_const, pm4); 2317 break; 2318 2319 default: 2320 R600_ERR("unsupported %d\n", shader); 2321 } 2322 2323 if (cb->buffer != &rbuffer->b.b) 2324 si_resource_reference(&rbuffer, NULL); 2325 } 2326 2327 /* 2328 * Vertex elements & buffers 2329 */ 2330 2331 static void *si_create_vertex_elements(struct pipe_context *ctx, 2332 unsigned count, 2333 const struct pipe_vertex_element *elements) 2334 { 2335 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element); 2336 int i; 2337 2338 assert(count < PIPE_MAX_ATTRIBS); 2339 if (!v) 2340 return NULL; 2341 2342 v->count = count; 2343 for (i = 0; i < count; ++i) { 2344 const struct util_format_description *desc; 2345 unsigned data_format, num_format; 2346 int first_non_void; 2347 2348 desc = util_format_description(elements[i].src_format); 2349 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format); 2350 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format, 2351 desc, first_non_void); 2352 2353 switch (desc->channel[first_non_void].type) { 2354 case UTIL_FORMAT_TYPE_FIXED: 2355 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */ 2356 break; 2357 case UTIL_FORMAT_TYPE_SIGNED: 2358 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM; 2359 break; 2360 case UTIL_FORMAT_TYPE_UNSIGNED: 2361 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM; 2362 break; 2363 case UTIL_FORMAT_TYPE_FLOAT: 2364 default: 2365 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT; 2366 } 2367 2368 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) | 2369 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) | 2370 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) | 2371 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) | 2372 S_008F0C_NUM_FORMAT(num_format) | 2373 S_008F0C_DATA_FORMAT(data_format); 2374 } 2375 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count); 2376 2377 return v; 2378 } 2379 2380 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state) 2381 { 2382 struct r600_context *rctx = (struct r600_context *)ctx; 2383 struct si_vertex_element *v = (struct si_vertex_element*)state; 2384 2385 rctx->vertex_elements = v; 2386 } 2387 2388 static void si_delete_vertex_element(struct pipe_context *ctx, void *state) 2389 { 2390 struct r600_context *rctx = (struct r600_context *)ctx; 2391 2392 if (rctx->vertex_elements == state) 2393 rctx->vertex_elements = NULL; 2394 FREE(state); 2395 } 2396 2397 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 2398 const struct pipe_vertex_buffer *buffers) 2399 { 2400 struct r600_context *rctx = (struct r600_context *)ctx; 2401 2402 util_copy_vertex_buffers(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, count); 2403 } 2404 2405 static void si_set_index_buffer(struct pipe_context *ctx, 2406 const struct pipe_index_buffer *ib) 2407 { 2408 struct r600_context *rctx = (struct r600_context *)ctx; 2409 2410 if (ib) { 2411 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer); 2412 memcpy(&rctx->index_buffer, ib, sizeof(*ib)); 2413 } else { 2414 pipe_resource_reference(&rctx->index_buffer.buffer, NULL); 2415 } 2416 } 2417 2418 /* 2419 * Misc 2420 */ 2421 static void si_set_polygon_stipple(struct pipe_context *ctx, 2422 const struct pipe_poly_stipple *state) 2423 { 2424 } 2425 2426 static void si_texture_barrier(struct pipe_context *ctx) 2427 { 2428 struct r600_context *rctx = (struct r600_context *)ctx; 2429 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 2430 2431 si_pm4_inval_texture_cache(pm4); 2432 si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs); 2433 si_pm4_set_state(rctx, texture_barrier, pm4); 2434 } 2435 2436 void si_init_state_functions(struct r600_context *rctx) 2437 { 2438 rctx->context.create_blend_state = si_create_blend_state; 2439 rctx->context.bind_blend_state = si_bind_blend_state; 2440 rctx->context.delete_blend_state = si_delete_blend_state; 2441 rctx->context.set_blend_color = si_set_blend_color; 2442 2443 rctx->context.create_rasterizer_state = si_create_rs_state; 2444 rctx->context.bind_rasterizer_state = si_bind_rs_state; 2445 rctx->context.delete_rasterizer_state = si_delete_rs_state; 2446 2447 rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state; 2448 rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state; 2449 rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state; 2450 rctx->custom_dsa_flush = si_create_db_flush_dsa(rctx); 2451 2452 rctx->context.set_clip_state = si_set_clip_state; 2453 rctx->context.set_scissor_state = si_set_scissor_state; 2454 rctx->context.set_viewport_state = si_set_viewport_state; 2455 rctx->context.set_stencil_ref = si_set_pipe_stencil_ref; 2456 2457 rctx->context.set_framebuffer_state = si_set_framebuffer_state; 2458 2459 rctx->context.create_vs_state = si_create_vs_state; 2460 rctx->context.create_fs_state = si_create_fs_state; 2461 rctx->context.bind_vs_state = si_bind_vs_shader; 2462 rctx->context.bind_fs_state = si_bind_ps_shader; 2463 rctx->context.delete_vs_state = si_delete_vs_shader; 2464 rctx->context.delete_fs_state = si_delete_ps_shader; 2465 2466 rctx->context.create_sampler_state = si_create_sampler_state; 2467 rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler; 2468 rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler; 2469 rctx->context.delete_sampler_state = si_delete_sampler_state; 2470 2471 rctx->context.create_sampler_view = si_create_sampler_view; 2472 rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view; 2473 rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view; 2474 rctx->context.sampler_view_destroy = si_sampler_view_destroy; 2475 2476 rctx->context.set_sample_mask = si_set_sample_mask; 2477 2478 rctx->context.set_constant_buffer = si_set_constant_buffer; 2479 2480 rctx->context.create_vertex_elements_state = si_create_vertex_elements; 2481 rctx->context.bind_vertex_elements_state = si_bind_vertex_elements; 2482 rctx->context.delete_vertex_elements_state = si_delete_vertex_element; 2483 rctx->context.set_vertex_buffers = si_set_vertex_buffers; 2484 rctx->context.set_index_buffer = si_set_index_buffer; 2485 2486 rctx->context.create_stream_output_target = si_create_so_target; 2487 rctx->context.stream_output_target_destroy = si_so_target_destroy; 2488 rctx->context.set_stream_output_targets = si_set_so_targets; 2489 2490 rctx->context.texture_barrier = si_texture_barrier; 2491 rctx->context.set_polygon_stipple = si_set_polygon_stipple; 2492 2493 rctx->context.draw_vbo = si_draw_vbo; 2494 } 2495 2496 void si_init_config(struct r600_context *rctx) 2497 { 2498 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); 2499 2500 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL); 2501 si_pm4_cmd_add(pm4, 0x80000000); 2502 si_pm4_cmd_add(pm4, 0x80000000); 2503 si_pm4_cmd_end(pm4, false); 2504 2505 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0); 2506 2507 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0); 2508 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0); 2509 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0); 2510 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0); 2511 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0); 2512 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0); 2513 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0); 2514 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0); 2515 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0); 2516 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0); 2517 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0); 2518 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0); 2519 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0); 2520 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0); 2521 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); 2522 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0); 2523 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); 2524 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM, 2525 S_028AA8_SWITCH_ON_EOP(1) | 2526 S_028AA8_PARTIAL_VS_WAVE_ON(1) | 2527 S_028AA8_PRIMGROUP_SIZE(63)); 2528 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000); 2529 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); 2530 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1); 2531 2532 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0); 2533 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210); 2534 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98); 2535 2536 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000); 2537 2538 si_pm4_set_state(rctx, init, pm4); 2539 } 2540
