/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGDumper.cpp | 42 if (getOpcode() < ISD::BUILTIN_OP_END) 60 case ISD::DELETED_NODE: return "<<Deleted Node!>>"; 62 case ISD::PREFETCH: return "Prefetch"; 63 case ISD::ATOMIC_FENCE: return "AtomicFence"; 64 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; 65 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: return "AtomicCmpSwapWithSuccess"; 66 case ISD::ATOMIC_SWAP: return "AtomicSwap"; 67 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; 68 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; 69 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd" [all...] |
LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition 16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the 18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC; 22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR, 201 if (Op.getOpcode() == ISD::LOAD) { 203 ISD::LoadExtType ExtType = LD->getExtensionType(); 204 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) 229 } else if (Op.getOpcode() == ISD::STORE) { 247 } else if (Op.getOpcode() == ISD::MSCATTER || Op.getOpcode() == ISD::MSTORE [all...] |
LegalizeIntegerTypes.cpp | 52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; 53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; 54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; 55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; 56 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break; 57 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; 58 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; 59 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; 60 case ISD::CONVERT_RNDSAT: 62 case ISD::CTLZ_ZERO_UNDEF [all...] |
LegalizeDAG.cpp | 272 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && 286 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx, 316 assert(ST->getAddressingMode() == ISD::UNINDEXED && 333 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); 375 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 377 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 387 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 399 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); 416 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 425 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr [all...] |
TargetLowering.cpp | 125 ISD::CondCode &CCCode, 134 case ISD::SETEQ: 135 case ISD::SETOEQ: 139 case ISD::SETNE: 140 case ISD::SETUNE: 144 case ISD::SETGE: 145 case ISD::SETOGE: 149 case ISD::SETLT: 150 case ISD::SETOLT: 154 case ISD::SETLE [all...] |
DAGCombiner.cpp | 136 if (N->getOpcode() == ISD::HANDLENODE) 195 /// \brief Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed 198 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced. 216 ISD::NodeType ExtType); 337 SDValue N3, ISD::CondCode CC, 339 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 573 if (Op.getOpcode() == ISD::FNEG) return 2; 583 case ISD::ConstantFP: 587 case ISD::FADD: 593 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()) [all...] |
LegalizeVectorTypes.cpp | 51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; 52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; 53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; 54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; 55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; 56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; 57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; 58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; 59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; 60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break [all...] |
/external/llvm/lib/Target/X86/ |
X86TargetTransformInfo.cpp | 95 int ISD = TLI->InstructionOpcodeToISD(Opcode); 96 assert(ISD && "Invalid opcode"); 98 if (ISD == ISD::SDIV && 119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence 122 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence 123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence 124 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence 129 if (const auto *Entry = CostTableLookup(AVX2UniformConstCostTable, ISD, [all...] |
X86CallingConv.h | 26 ISD::ArgFlagsTy &ArgFlags, 37 CCValAssign::LocInfo &, ISD::ArgFlagsTy &,
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X86IntrinsicsInfo.h | 259 X86_INTRINSIC_DATA(avx2_pmaxs_b, INTR_TYPE_2OP, ISD::SMAX, 0), 260 X86_INTRINSIC_DATA(avx2_pmaxs_d, INTR_TYPE_2OP, ISD::SMAX, 0), 261 X86_INTRINSIC_DATA(avx2_pmaxs_w, INTR_TYPE_2OP, ISD::SMAX, 0), 262 X86_INTRINSIC_DATA(avx2_pmaxu_b, INTR_TYPE_2OP, ISD::UMAX, 0), 263 X86_INTRINSIC_DATA(avx2_pmaxu_d, INTR_TYPE_2OP, ISD::UMAX, 0), 264 X86_INTRINSIC_DATA(avx2_pmaxu_w, INTR_TYPE_2OP, ISD::UMAX, 0), 265 X86_INTRINSIC_DATA(avx2_pmins_b, INTR_TYPE_2OP, ISD::SMIN, 0), 266 X86_INTRINSIC_DATA(avx2_pmins_d, INTR_TYPE_2OP, ISD::SMIN, 0), 267 X86_INTRINSIC_DATA(avx2_pmins_w, INTR_TYPE_2OP, ISD::SMIN, 0), 268 X86_INTRINSIC_DATA(avx2_pminu_b, INTR_TYPE_2OP, ISD::UMIN, 0) [all...] |
/external/llvm/include/llvm/Target/ |
CostTable.h | 25 int ISD; 32 int ISD, MVT Ty) { 35 return ISD == Entry.ISD && Ty == Entry.Type; }); 45 int ISD; 55 int ISD, MVT Dst, MVT Src) { 58 return ISD == Entry.ISD && Src == Entry.Src &&
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/external/llvm/lib/Target/ARM/ |
ARMTargetTransformInfo.cpp | 51 int ISD = TLI->InstructionOpcodeToISD(Opcode); 52 assert(ISD && "Invalid opcode"); 57 { ISD::FP_ROUND, MVT::v2f64, 2 }, 58 { ISD::FP_EXTEND, MVT::v2f32, 2 }, 59 { ISD::FP_EXTEND, MVT::v4f32, 4 } 62 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND || 63 ISD == ISD::FP_EXTEND)) { 65 if (const auto *Entry = CostTableLookup(NEONFltDblTbl, ISD, LT.second) [all...] |
ARMISelLowering.cpp | 91 setOperationAction(ISD::LOAD, VT, Promote); 92 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT); 94 setOperationAction(ISD::STORE, VT, Promote); 95 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT); 100 setOperationAction(ISD::SETCC, VT, Custom); 101 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); 102 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); 104 setOperationAction(ISD::SINT_TO_FP, VT, Custom); 105 setOperationAction(ISD::UINT_TO_FP, VT, Custom); 106 setOperationAction(ISD::FP_TO_SINT, VT, Custom) [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCCallingConv.h | 24 CCValAssign::LocInfo &, ISD::ArgFlagsTy &,
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/external/llvm/lib/Target/AArch64/ |
AArch64TargetTransformInfo.cpp | 180 int ISD = TLI->InstructionOpcodeToISD(Opcode); 181 assert(ISD && "Invalid opcode"); 191 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 192 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, 193 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, 194 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, 197 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 198 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 199 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, 200 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 } [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
AMDILISelLowering.cpp | 110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom); 111 setOperationAction(ISD::SUBE, VT, Expand); 112 setOperationAction(ISD::SUBC, VT, Expand); 113 setOperationAction(ISD::ADDE, VT, Expand); 114 setOperationAction(ISD::ADDC, VT, Expand); 115 setOperationAction(ISD::BRCOND, VT, Custom); 116 setOperationAction(ISD::BR_JT, VT, Expand); 117 setOperationAction(ISD::BRIND, VT, Expand); 119 setOperationAction(ISD::SREM, VT, Expand); 120 setOperationAction(ISD::SMUL_LOHI, VT, Expand) [all...] |
AMDGPUISelLowering.cpp | 31 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 35 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 36 setOperationAction(ISD::FEXP2, MVT::f32, Legal); 37 setOperationAction(ISD::FRINT, MVT::f32, Legal); 39 setOperationAction(ISD::UDIV, MVT::i32, Expand); 40 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); 41 setOperationAction(ISD::UREM, MVT::i32, Expand); 52 const SmallVectorImpl<ISD::InputArg> &Ins, 68 const SmallVectorImpl<ISD::OutputArg> &Outs, 89 case ISD::SDIV: return LowerSDIV(Op, DAG) [all...] |
/external/llvm/lib/Target/Mips/ |
MipsCCState.h | 33 void PreAnalyzeCallResultForF128(const SmallVectorImpl<ISD::InputArg> &Ins, 38 void PreAnalyzeReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs); 43 PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, 50 PreAnalyzeFormalArgumentsForF128(const SmallVectorImpl<ISD::InputArg> &Ins); 59 /// See ISD::OutputArg::IsFixed, 73 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, 87 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, 90 SmallVectorImpl<ISD::ArgFlagsTy> &Flags, 93 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, 101 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins [all...] |
/external/llvm/include/llvm/CodeGen/ |
SelectionDAGNodes.h | 66 namespace ISD { 86 /// and all operands of the specified node are ISD::UNDEF. 88 } // end llvm:ISD namespace 439 /// are the opcode values in the ISD and <target>ISD namespaces. For 444 /// \<target\>ISD namespace). 445 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; } 448 /// memory-referencing opcode (in the \<target\>ISD namespace and 451 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE; 455 bool isUndef() const { return NodeType == ISD::UNDEF; [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | 107 ISD::ArgFlagsTy ArgFlags, CCState &State); 112 ISD::ArgFlagsTy ArgFlags, CCState &State); 117 ISD::ArgFlagsTy ArgFlags, CCState &State); 122 ISD::ArgFlagsTy ArgFlags, CCState &State); 127 ISD::ArgFlagsTy ArgFlags, CCState &State); 132 ISD::ArgFlagsTy ArgFlags, CCState &State); 137 ISD::ArgFlagsTy ArgFlags, CCState &State); 142 ISD::ArgFlagsTy ArgFlags, CCState &State); 147 ISD::ArgFlagsTy ArgFlags, CCState &State) { 221 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) [all...] |
/external/llvm/lib/Target/AMDGPU/ |
AMDGPUISelLowering.cpp | 36 ISD::ArgFlagsTy ArgFlags, CCState &State) { 68 setOperationAction(ISD::Constant, MVT::i32, Legal); 69 setOperationAction(ISD::Constant, MVT::i64, Legal); 70 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); 71 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); 73 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 74 setOperationAction(ISD::BRIND, MVT::Other, Expand); 77 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 80 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 84 setOperationAction(ISD::FCEIL, MVT::f32, Legal) [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXTargetTransformInfo.cpp | 99 int ISD = TLI->InstructionOpcodeToISD(Opcode); 101 switch (ISD) { 105 case ISD::ADD: 106 case ISD::MUL: 107 case ISD::XOR: 108 case ISD::OR: 109 case ISD::AND:
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/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 77 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); 78 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 81 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); 82 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); 83 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); 84 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); 85 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); 91 setOperationAction(ISD::SRA, MVT::i8, Custom); 92 setOperationAction(ISD::SHL, MVT::i8, Custom); 93 setOperationAction(ISD::SRL, MVT::i8, Custom) [all...] |
/external/llvm/lib/CodeGen/ |
TargetLoweringBase.cpp | 675 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) 676 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) 677 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) 678 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) 679 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) 680 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) 681 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) 682 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) 683 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) 684 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX [all...] |
Analysis.cpp | 159 /// getFCmpCondCode - Return the ISD condition code corresponding to 163 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { 165 case FCmpInst::FCMP_FALSE: return ISD::SETFALSE; 166 case FCmpInst::FCMP_OEQ: return ISD::SETOEQ; 167 case FCmpInst::FCMP_OGT: return ISD::SETOGT; 168 case FCmpInst::FCMP_OGE: return ISD::SETOGE; 169 case FCmpInst::FCMP_OLT: return ISD::SETOLT; 170 case FCmpInst::FCMP_OLE: return ISD::SETOLE; 171 case FCmpInst::FCMP_ONE: return ISD::SETONE; 172 case FCmpInst::FCMP_ORD: return ISD::SETO [all...] |