| /art/compiler/optimizing/ |
| code_generator_mips.cc | 229 __ LoadConst32(calling_convention.GetRegisterAt(0), cls_->GetTypeIndex());
288 __ LoadConst32(calling_convention.GetRegisterAt(0), string_index);
[all...] |
| intrinsics_mips.cc | 285 __ LoadConst32(AT, 0x00FF00FF);
296 __ LoadConst32(AT, 0x0F0F0F0F);
302 __ LoadConst32(AT, 0x33333333);
308 __ LoadConst32(AT, 0x55555555);
344 __ LoadConst32(AT, 0x00FF00FF);
362 __ LoadConst32(AT, 0x0F0F0F0F);
373 __ LoadConst32(AT, 0x33333333);
384 __ LoadConst32(AT, 0x55555555);
542 __ LoadConst32(TMP, 32);
549 __ LoadConst32(TMP, 32)
[all...] |
| code_generator_mips64.cc | 188 __ LoadConst32(calling_convention.GetRegisterAt(0), cls_->GetTypeIndex());
243 __ LoadConst32(calling_convention.GetRegisterAt(0), string_index);
689 __ LoadConst32(gpr, value);
768 __ LoadConst32(gpr, value);
[all...] |
| intrinsics_mips64.cc | [all...] |
| /art/compiler/utils/mips/ |
| assembler_mips.cc | [all...] |
| assembler_mips.h | 356 void LoadConst32(Register rd, int32_t value);
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64.cc | 1035 void Mips64Assembler::LoadConst32(GpuRegister rd, int32_t value) {
[all...] |
| assembler_mips64.h | 324 void LoadConst32(GpuRegister rd, int32_t value);
|
