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    Searched refs:MI_FLUSH (Results 1 - 7 of 7) sorted by null

  /external/mesa3d/src/mesa/drivers/dri/intel/
intel_reg.h 36 #define MI_FLUSH (CMD_MI | (4 << 23))
58 * PIPE_CONTROL operation, a combination MI_FLUSH and register write with
intel_batchbuffer.c 375 * already flushed (e.g., via a preceding MI_FLUSH).
540 OUT_BATCH(MI_FLUSH);
  /external/mesa3d/src/gallium/drivers/i915/
i915_state_emit.c 68 OUT_BATCH(MI_FLUSH | FLUSH_MAP_CACHE);
70 OUT_BATCH(MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE);
i915_reg.h     [all...]
  /external/drm_gralloc/
gralloc_drm_intel.c 45 #define MI_FLUSH (0x04 << 23)
  /external/mesa3d/src/mesa/drivers/dri/i965/
brw_misc_state.c 152 OUT_BATCH(MI_FLUSH);
838 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
  /external/mesa3d/src/mesa/drivers/dri/i915/
i915_vtbl.c 671 /* When changing drawing rectangle offset, an MI_FLUSH is first required. */
673 state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE;

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