| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 102 // normally expanded to the sequence SRA + SRL + ADD + SRA.
119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle.
137 { ISD::SRA, MVT::v16i32, 1 },
140 { ISD::SRA, MVT::v8i64, 1 },
153 { ISD::SRA, MVT::v4i32, 1 },
156 { ISD::SRA, MVT::v8i32, 1 },
180 { ISD::SRA, MVT::v16i8, 2 },
183 { ISD::SRA, MVT::v8i16, 2 },
186 { ISD::SRA, MVT::v4i32, 2 }
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr;
|
| /prebuilts/go/darwin-x86/pkg/bootstrap/src/bootstrap/internal/obj/arm/ |
| anames.go | 66 "SRA",
|
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/arm/ |
| anames.go | 63 "SRA",
|
| /prebuilts/go/linux-x86/src/cmd/internal/obj/arm/ |
| anames.go | 63 "SRA",
|
| /external/pcre/dist/sljit/ |
| sljitNativeSPARC_32.c | 60 return push_inst(compiler, SRA | D(dst) | S1(dst) | IMM(24), DR(dst));
71 return push_inst(compiler, (op == SLJIT_MOV_SH ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst));
112 FAIL_IF(push_inst(compiler, SRA | D(TMP_REG1) | S1(dst) | IMM(31), DR(TMP_REG1)));
134 FAIL_IF(push_inst(compiler, SRA | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst)));
|
| sljitNativeMIPS_32.c | 91 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(24), DR(dst));
109 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(16), DR(dst));
312 FAIL_IF(push_inst(compiler, SRA | T(dst) | DA(UGREATER_FLAG) | SH_IMM(31), UGREATER_FLAG));
336 EMIT_SHIFT(SRA, SRAV);
|
| sljitNativeMIPS_64.c | 407 FAIL_IF(push_inst(compiler, SELECT_OP(DSRA32, SRA) | T(dst) | DA(UGREATER_FLAG) | SH_IMM(31), UGREATER_FLAG));
431 EMIT_SHIFT(DSRA, DSRA32, SRA, DSRAV, SRAV);
|
| /prebuilts/go/linux-x86/pkg/bootstrap/src/bootstrap/internal/obj/arm/ |
| anames.go | 66 "SRA",
|
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 399 case ASR: mMips->SRA(tmpReg, amode.reg, amode.value); break;
510 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
542 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
[all...] |
| MIPS64Assembler.cpp | 388 case ASR: mMips->SRA(tmpReg, amode.reg, amode.value); break;
511 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
538 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break;
1085 mMips->SRA(R_at, Rm, 16);
1093 mMips->SRA(R_at2, Rs, 16);
[all...] |
| MIPSAssembler.h | 318 void SRA(int Rd, int Rt, int shft);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts.
65 SHL, SRA, SRL
|
| MSP430ISelLowering.cpp | 91 setOperationAction(ISD::SRA, MVT::i8, Custom);
94 setOperationAction(ISD::SRA, MVT::i16, Custom);
188 case ISD::SRA: return LowerShifts(Op, DAG);
750 case ISD::SRA:
751 return DAG.getNode(MSP430ISD::SRA, dl,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 86 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
673 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
[all...] |
| LegalizeVectorOps.cpp | 18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
279 case ISD::SRA:
610 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
788 // Make sure that the SRA and SHL instructions are available.
789 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
802 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
846 return DAG.getNode(ISD::SRA, DL, VT,
[all...] |
| DAGCombiner.cpp | [all...] |
| /external/valgrind/none/tests/mips64/ |
| shift_instructions.c | 10 SRA, SRAV, SRL, SRLV
177 case SRA:
178 TEST2("sra $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
179 TEST2("sra $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
180 TEST2("sra $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
181 TEST2("sra $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 336 SHL, SRA, SRL, ROTL, ROTR,
405 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 442 Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift);
512 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
|
| /external/v8/src/mips/ |
| constants-mips.h | 401 SRA = ((0U << 3) + 3),
914 FunctionFieldToBitNumber(SRL) | FunctionFieldToBitNumber(SRA) |
[all...] |
| /external/v8/src/mips64/ |
| constants-mips64.h | 397 SRA = ((0U << 3) + 3),
964 FunctionFieldToBitNumber(DSRL32) | FunctionFieldToBitNumber(SRA) |
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | [all...] |
| AMDGPUISelDAGToDAG.cpp | 506 case ISD::SRA:
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 94 SRL, SRA, SHL,
96 /// The combination of sra[wd]i and addze used to implemented signed
[all...] |
