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      1 #include <stdio.h>
      2 #include "const.h"
      3 #include "macro_int.h"
      4 
      5 typedef enum {
      6     DROTR=0,  DROTR32,   DROTRV,    DSLL,
      7     DSLL32,   DSLLV,     DSRA,      DSRA32,
      8     DSRAV,    DSRL,      DSRL32,    DSRLV,
      9     ROTR,     ROTRV,     SLL,       SLLV,
     10     SRA,      SRAV,      SRL,       SRLV
     11 } logical_op;
     12 
     13 int main()
     14 {
     15    logical_op op;
     16    int i;
     17    init_reg_val2();
     18    for (op = DROTR; op <= SRLV; op++) {
     19       for (i = 0; i < N; i++) {
     20          switch(op) {
     21             case DROTR:
     22                /* Release 2 Only */
     23 #if (__mips == 64) && (__mips_isa_rev >= 2)
     24                TEST2("drotr $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
     25                TEST2("drotr $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
     26                TEST2("drotr $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
     27                TEST2("drotr $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
     28                TEST2("drotr $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
     29                TEST2("drotr $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
     30                TEST2("drotr $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
     31                TEST2("drotr $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
     32 #endif
     33                break;
     34             case DROTR32:
     35                /* Release 2 Only */
     36 #if (__mips == 64) && (__mips_isa_rev >= 2)
     37                TEST2("drotr32 $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
     38                TEST2("drotr32 $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
     39                TEST2("drotr32 $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
     40                TEST2("drotr32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
     41                TEST2("drotr32 $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
     42                TEST2("drotr32 $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
     43                TEST2("drotr32 $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
     44                TEST2("drotr32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
     45 #endif
     46                break;
     47             case DROTRV:
     48                /* Release 2 Only */
     49 #if (__mips == 64) && (__mips_isa_rev >= 2)
     50                TEST1("drotrv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
     51                                              t0, t1, t2);
     52                TEST1("drotrv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
     53                                              s0, s1, s2);
     54 #endif
     55                break;
     56             case DSLL:
     57                TEST2("dsll $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
     58                TEST2("dsll $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
     59                TEST2("dsll $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
     60                TEST2("dsll $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
     61                TEST2("dsll $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
     62                TEST2("dsll $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
     63                TEST2("dsll $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
     64                TEST2("dsll $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
     65                break;
     66 
     67             case DSLL32:
     68                TEST2("dsll32 $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
     69                TEST2("dsll32 $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
     70                TEST2("dsll32 $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
     71                TEST2("dsll32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
     72                TEST2("dsll32 $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
     73                TEST2("dsll32 $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
     74                TEST2("dsll32 $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
     75                TEST2("dsll32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
     76                break;
     77 
     78             case DSLLV:
     79                TEST1("dsllv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
     80                                             t0, t1, t2);
     81                TEST1("dsllv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
     82                                             s0, s1, s2);
     83                break;
     84 
     85             case DSRA:
     86                TEST2("dsra $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
     87                TEST2("dsra $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
     88                TEST2("dsra $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
     89                TEST2("dsra $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
     90                TEST2("dsra $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
     91                TEST2("dsra $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
     92                TEST2("dsra $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
     93                TEST2("dsra $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
     94                break;
     95 
     96             case DSRA32:
     97                TEST2("dsra32 $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
     98                TEST2("dsra32 $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
     99                TEST2("dsra32 $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
    100                TEST2("dsra32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
    101                TEST2("dsra32 $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
    102                TEST2("dsra32 $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
    103                TEST2("dsra32 $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
    104                TEST2("dsra32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
    105                break;
    106 
    107             case DSRAV:
    108                TEST1("dsrav $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
    109                                             t0, t1, t2);
    110                TEST1("dsrav $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
    111                                             s0, s1, s2);
    112                break;
    113 
    114             case DSRL:
    115                TEST2("dsrl $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
    116                TEST2("dsrl $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
    117                TEST2("dsrl $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
    118                TEST2("dsrl $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
    119                TEST2("dsrl $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
    120                TEST2("dsrl $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
    121                TEST2("dsrl $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
    122                TEST2("dsrl $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
    123                break;
    124 
    125             case DSRL32:
    126                TEST2("dsrl32 $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
    127                TEST2("dsrl32 $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
    128                TEST2("dsrl32 $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
    129                TEST2("dsrl32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
    130                TEST2("dsrl32 $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
    131                TEST2("dsrl32 $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
    132                TEST2("dsrl32 $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
    133                TEST2("dsrl32 $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
    134                break;
    135 
    136             case DSRLV:
    137                TEST1("dsrlv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
    138                                             t0, t1, t2);
    139                TEST1("dsrlv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
    140                                             s0, s1, s2);
    141                break;
    142 
    143             case ROTR:
    144                /* Release 2 Only */
    145 #if (__mips == 64) && (__mips_isa_rev >= 2)
    146                TEST2("rotr $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
    147                TEST2("rotr $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
    148                TEST2("rotr $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
    149                TEST2("rotr $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
    150 #endif
    151                break;
    152             case ROTRV:
    153                /* Release 2 Only */
    154 #if (__mips == 64) && (__mips_isa_rev >= 2)
    155                TEST1("rotrv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
    156                                             t0, t1, t2);
    157 #endif
    158                break;
    159             case SLL:
    160                TEST2("sll $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
    161                TEST2("sll $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
    162                TEST2("sll $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
    163                TEST2("sll $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
    164                TEST2("sll $t0, $t1, 0x00", reg_val2[i], 0x00, t0, t1);
    165                TEST2("sll $t2, $t3, 0x1f", reg_val2[i], 0x1f, t2, t3);
    166                TEST2("sll $a0, $a1, 0x0f", reg_val2[i], 0x0f, a0, a1);
    167                TEST2("sll $s0, $s1, 0x03", reg_val2[i], 0x03, s0, s1);
    168                break;
    169 
    170             case SLLV:
    171                TEST1("sllv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
    172                                            t0, t1, t2);
    173                TEST1("sllv $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
    174                                            s0, s1, s2);
    175                break;
    176 
    177             case SRA:
    178                TEST2("sra $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
    179                TEST2("sra $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
    180                TEST2("sra $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
    181                TEST2("sra $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
    182                break;
    183 
    184             case SRAV:
    185                TEST1("srav $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
    186                                            t0, t1, t2);
    187                break;
    188 
    189             case SRL:
    190                TEST2("srl $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
    191                TEST2("srl $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
    192                TEST2("srl $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
    193                TEST2("srl $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
    194                break;
    195 
    196             case SRLV:
    197                TEST1("srlv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
    198                                            t0, t1, t2);
    199                break;
    200 
    201          }
    202       }
    203    }
    204    return 0;
    205 }
    206