| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.cpp | 54 .addReg(SrcReg, getKillRegState(KillSrc)));
64 .addReg(SrcReg, getKillRegState(KillSrc));
91 .addReg(SrcReg, getKillRegState(isKill))
|
| MLxExpansionPass.cpp | 294 .addReg(Src1Reg, getKillRegState(Src1Kill))
295 .addReg(Src2Reg, getKillRegState(Src2Kill));
305 MIB.addReg(TmpReg, getKillRegState(true))
306 .addReg(AccReg, getKillRegState(AccKill));
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
|
| ARMLoadStoreOptimizer.cpp | 690 .addReg(Base, getKillRegState(KillOldBase));
693 .addReg(Base, getKillRegState(KillOldBase))
703 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset/4)
708 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset)
712 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset)
752 .addReg(Base, getKillRegState(BaseKill));
762 MIB.addReg(Base, getKillRegState(BaseKill));
768 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second));
788 MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second))
789 .addReg(Regs[1].first, getKillRegState(Regs[1].second))
[all...] |
| ARMBaseInstrInfo.cpp | 677 MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
695 MIB.addReg(SrcReg, getKillRegState(KillSrc));
711 .addReg(SrcReg, getKillRegState(KillSrc))));
732 MIB.addReg(SrcReg, getKillRegState(KillSrc));
734 MIB.addReg(SrcReg, getKillRegState(KillSrc));
864 .addReg(SrcReg, getKillRegState(isKill))
868 .addReg(SrcReg, getKillRegState(isKill))
876 .addReg(SrcReg, getKillRegState(isKill))
881 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
892 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 298 .addReg(SrcReg, getKillRegState(KillSrc));
306 .addReg(SrcReg, getKillRegState(KillSrc));
310 .addReg(SrcReg, getKillRegState(KillSrc));
321 .addReg(SrcReg, getKillRegState(KillSrc));
338 .addReg(SrcReg, getKillRegState(KillSrc));
342 .addReg(SrcReg, getKillRegState(KillSrc));
386 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
389 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
392 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
395 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstrInfo.cpp | 49 .addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/llvm/lib/Target/BPF/ |
| BPFInstrInfo.cpp | 40 .addReg(SrcReg, getKillRegState(KillSrc));
56 .addReg(SrcReg, getKillRegState(IsKill))
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 287 .addReg(Src, getKillRegState(IsKill));
357 .addReg(Src0, getKillRegState(true), SubReg0)
358 .addReg(Src1, getKillRegState(true), SubReg1);
|
| AArch64InstrInfo.cpp | [all...] |
| AArch64FastISel.cpp | 349 ResultReg).addReg(ZeroReg, getKillRegState(true));
387 .addReg(TmpReg, getKillRegState(true));
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
59 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
102 .addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonNewValueJump.cpp | 644 .addReg(cmpReg1, getKillRegState(MO1IsKill))
645 .addReg(cmpOp2, getKillRegState(MO2IsKill))
655 .addReg(cmpReg1, getKillRegState(MO1IsKill))
661 .addReg(cmpReg1, getKillRegState(MO1IsKill))
|
| HexagonStoreWidening.cpp | 442 .addReg(MR.getReg(), getKillRegState(MR.isKill()))
464 .addReg(MR.getReg(), getKillRegState(MR.isKill()))
|
| HexagonCopyToCombine.cpp | 641 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
688 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
737 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill());
738 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill());
|
| HexagonInstrInfo.cpp | 638 addReg(SrcReg, getKillRegState(KillSrc));
644 addReg(SrcReg, getKillRegState(KillSrc));
650 addReg(SrcReg, getKillRegState(KillSrc));
655 addReg(SrcReg, getKillRegState(KillSrc));
661 getKillRegState(KillSrc)).
663 getKillRegState(KillSrc));
669 addReg(SrcReg, getKillRegState(KillSrc));
686 getKillRegState(KillSrc));
690 getKillRegState(KillSrc));
719 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 78 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
114 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
148 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
191 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
|
| XCoreInstrInfo.cpp | 341 .addReg(SrcReg, getKillRegState(KillSrc))
353 .addReg(SrcReg, getKillRegState(KillSrc));
376 .addReg(SrcReg, getKillRegState(isKill))
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 382 .addReg(Reg2, getKillRegState(Reg2IsKill))
383 .addReg(Reg1, getKillRegState(Reg1IsKill))
864 .addReg(CRReg), getKillRegState(KillSrc);
876 .addReg(SrcReg), getKillRegState(KillSrc);
881 .addReg(SrcReg), getKillRegState(KillSrc);
[all...] |
| PPCRegisterInfo.cpp | 390 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
398 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
415 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
423 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
483 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
570 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
660 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
[all...] |
| PPCFrameLowering.cpp | 797 .addReg(TempReg, getKillRegState(true))
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 108 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
129 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
173 MIB.addReg(SrcReg, getKillRegState(KillSrc));
244 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
558 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
559 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
569 unsigned KillSrc = getKillRegState(Src.isKill());
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 184 .addReg(SrcReg, getKillRegState(KillSrc));
190 .addReg(SrcReg, getKillRegState(KillSrc))
589 .addReg(SrcReg, getKillRegState(KillSrc));
603 .addReg(SrcReg, getKillRegState(isKill)),
715 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
747 .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg())
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 64 .addReg(SrcReg, getKillRegState(KillSrc));
|
