| /external/llvm/lib/Target/SystemZ/ |
| SystemZFrameLowering.cpp | 71 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
98 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
129 const TargetRegisterInfo *TRI) const {
207 &SystemZ::FP64BitRegClass, TRI);
218 const TargetRegisterInfo *TRI) const {
233 &SystemZ::FP64BitRegClass, TRI);
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| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 203 const TargetRegisterInfo &TRI;
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| CallingConvLower.h | 199 const TargetRegisterInfo &TRI;
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| /external/llvm/lib/CodeGen/ |
| MIRPrinter.cpp | 80 const TargetRegisterInfo *TRI);
90 const TargetRegisterInfo *TRI);
120 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
124 void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
147 const TargetRegisterInfo *TRI) {
153 else if (Reg < TRI->getNumRegs())
154 OS << '%' << StringRef(TRI->getName(Reg)).lower();
160 const TargetRegisterInfo *TRI) {
162 printReg(Reg, OS, TRI);
199 const TargetRegisterInfo *TRI) {
[all...] |
| MachineCSE.cpp | 45 const TargetRegisterInfo *TRI;
145 // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
147 // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
195 if (!TRI->regsOverlap(MO.getReg(), Reg))
234 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
263 for (MCRegAliasIterator AI(PhysDefs[i], TRI, true); AI.isValid(); ++AI)
614 ImplicitDef, /*isKill=*/true, TRI))
715 TRI = MF.getSubtarget().getRegisterInfo();
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| EarlyIfConversion.cpp | 83 const TargetRegisterInfo *TRI;
157 TRI = MF.getSubtarget().getRegisterInfo();
160 LiveRegUnits.setUniverse(TRI->getNumRegUnits());
162 ClobberedRegUnits.resize(TRI->getNumRegUnits());
240 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
296 for (MCRegUnitIterator Units(Reg, TRI); Units.isValid(); ++Units)
304 for (MCRegUnitIterator Units(Reads.pop_back_val(), TRI); Units.isValid();
320 dbgs() << ' ' << PrintRegUnit(*i, TRI);
591 const TargetRegisterInfo *TRI;
794 TRI = STI.getRegisterInfo()
[all...] |
| MachineFunction.cpp | 382 const TargetRegisterInfo *TRI = getSubtarget().getRegisterInfo();
388 OS << PrintReg(I->first, TRI);
390 OS << " in " << PrintReg(I->second, TRI);
611 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
612 BitVector BV(TRI->getNumRegs());
619 for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
624 for (MCSubRegIterator S(I.getReg(), TRI, true); S.isValid(); ++S)
[all...] |
| PrologEpilogInserter.cpp | 81 // TRI->requiresFrameIndexScavenging() for the current function.
168 const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
173 RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : nullptr;
174 FrameIndexVirtualScavenging = TRI->requiresFrameIndexScavenging(Fn);
219 if (TRI->requiresRegisterScavenging(Fn) && FrameIndexVirtualScavenging)
443 const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
449 if (!TFI->spillCalleeSavedRegisters(*SaveBlock, I, CSI, TRI)) {
453 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
455 RC, TRI);
479 if (!TFI->restoreCalleeSavedRegisters(*MBB, I, CSI, TRI)) {
[all...] |
| RegAllocFast.cpp | 58 const TargetRegisterInfo *TRI;
125 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
131 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units)
240 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true);
285 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI)
286 << " in " << PrintReg(LR.PhysReg, TRI));
290 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
365 for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) {
380 assert((TRI->isSuperRegister(PhysReg, Alias) ||
381 TRI->isSuperRegister(Alias, PhysReg)) &
[all...] |
| RegAllocPBQP.cpp | 366 const TargetRegisterInfo &TRI =
385 if (TRI.regsOverlap(PRegN, PRegM)) {
545 static bool isACalleeSavedRegister(unsigned reg, const TargetRegisterInfo &TRI,
547 const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF);
549 if (TRI.regsOverlap(reg, CSR[i]))
560 const TargetRegisterInfo &TRI =
590 for (MCRegUnitIterator Units(PReg, &TRI); Units.isValid(); ++Units) {
617 if (isACalleeSavedRegister(VRegAllowed[i], TRI, MF))
637 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
638 (void)TRI;
[all...] |
| RegisterPressure.cpp | 45 const TargetRegisterInfo *TRI) {
49 dbgs() << TRI->getRegPressureSetName(i) << "=" << SetPressure[i] << '\n';
58 void RegisterPressure::dump(const TargetRegisterInfo *TRI) const {
60 dumpRegSetPressure(MaxSetPressure, TRI);
63 dbgs() << PrintVRegOrUnit(Reg, TRI) << " ";
67 dbgs() << PrintVRegOrUnit(Reg, TRI) << " ";
75 dumpRegSetPressure(CurrSetPressure, TRI);
77 P.dump(TRI);
80 void PressureDiff::dump(const TargetRegisterInfo &TRI) const {
85 dbgs() << sep << TRI.getRegPressureSetName(Change.getPSet()
[all...] |
| TailDuplication.cpp | 65 const TargetRegisterInfo *TRI;
140 TRI = MF.getSubtarget().getRegisterInfo();
147 if (MRI->tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF))
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 142 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
144 TLI->ParseConstraints(Fn->getParent()->getDataLayout(), TRI, CS);
151 TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
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| /external/llvm/lib/Target/AArch64/ |
| AArch64A57FPLoadBalancing.cpp | 117 const TargetRegisterInfo *TRI;
319 TRI = F.getRegInfo().getTargetRegisterInfo();
501 BitVector AvailableRegs = RS.getRegsAvailable(TRI->getRegClass(RegClassID));
505 AvailableRegs &= RS.getRegsAvailable(TRI->getRegClass(RegClassID));
514 MCRegAliasIterator AI(J.getReg(), TRI, /*IncludeSelf=*/true);
529 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));
554 DEBUG(dbgs() << " - Scavenged register: " << TRI->getName(Reg) << "\n");
630 << TRI->getName(DestReg) << " at " << *MI);
650 << TRI->getName(AccumReg) << " in MI " << *MI);
675 << TRI->getName(DestReg) << "\n")
[all...] |
| AArch64ConditionalCompares.cpp | 143 const TargetRegisterInfo *TRI;
195 TRI = MF.getSubtarget().getRegisterInfo();
354 MIOperands(I).analyzePhysReg(AArch64::NZCV, TRI);
425 if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) {
596 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF));
605 TII->getRegClass(MCID, 1, TRI, *MF));
652 TII->getRegClass(MCID, 0, TRI, *MF));
655 TII->getRegClass(MCID, 1, TRI, *MF));
725 const TargetRegisterInfo *TRI;
895 TRI = MF.getSubtarget().getRegisterInfo()
[all...] |
| AArch64CollectLOH.cpp | 288 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
354 for (MCRegAliasIterator AI(CurReg, TRI, true); AI.isValid(); ++AI) {
474 unsigned NbReg, const TargetRegisterInfo *TRI,
480 DEBUG(dbgs() << "*** Reg " << PrintReg(IdToReg[CurReg], TRI) << " ***\n");
[all...] |
| AArch64LoadStoreOptimizer.cpp | 87 const TargetRegisterInfo *TRI;
765 unsigned DstRegW = TRI->getSubReg(DstRegX, AArch64::sub_32);
807 const TargetRegisterInfo *TRI) {
816 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
820 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
890 if (FirstMI->modifiesRegister(BaseReg, TRI))
904 ModifiedRegs.resize(TRI->getNumRegs());
905 UsedRegs.resize(TRI->getNumRegs());
960 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 61 const TargetRegisterInfo *TRI;
151 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
160 if (!TRI->isVirtualRegister(SReg))
202 if (!TRI->isVirtualRegister(Reg))
225 if (!TRI->isVirtualRegister(DefReg)) {
261 if (TRI->isVirtualRegister(DPRReg) && TRI->isVirtualRegister(SPRReg)) {
311 if (!TRI->isVirtualRegister(OpReg))
355 if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
383 if (!TRI->isVirtualRegister(Reg))
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCopyToCombine.cpp | 61 const TargetRegisterInfo *TRI;
169 static bool areCombinableOperations(const TargetRegisterInfo *TRI,
207 const TargetRegisterInfo *TRI) {
208 return (UseReg && (I->modifiesRegister(UseReg, TRI))) ||
209 I->modifiesRegister(DestReg, TRI) ||
210 I->readsRegister(DestReg, TRI) ||
230 if (I2UseReg && I1->modifiesRegister(I2UseReg, TRI))
260 if (isUnsafeToMoveAcross(&*I, I2UseReg, I2DestReg, TRI)) {
267 I->readsRegister(KilledOperand, TRI))
273 bool Added = KillingInstr->addRegisterKilled(KilledOperand, TRI, true)
[all...] |
| HexagonGenPredicate.cpp | 51 PrintRegister(Register R, const TargetRegisterInfo &I) : Reg(R), TRI(I) {}
55 const TargetRegisterInfo &TRI;
60 return OS << PrintReg(PR.Reg.R, &PR.TRI, PR.Reg.S);
66 HexagonGenPredicate() : MachineFunctionPass(ID), TII(0), TRI(0), MRI(0) {
85 const HexagonRegisterInfo *TRI;
208 << PrintReg(Reg.R, TRI, Reg.S) << "\n");
212 DEBUG(dbgs() << "Dead reg: " << PrintReg(Reg.R, TRI, Reg.S) << '\n');
235 DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": " << PrintRegister(Reg, *TRI));
243 DEBUG(dbgs() << " -> " << PrintRegister(PR, *TRI) << '\n');
259 DEBUG(dbgs() << " -> !" << PrintRegister(Register(NewPR), *TRI) << '\n')
[all...] |
| HexagonStoreWidening.cpp | 55 const HexagonRegisterInfo *TRI;
450 const TargetRegisterClass *RC = TII->getRegClass(TfrD, 0, TRI, *MF);
600 TRI = ST.getRegisterInfo();
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| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 182 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
251 const TargetRegisterInfo *TRI, int64_t Offset) const {
632 const TargetRegisterInfo &TRI = getRegisterInfo();
657 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
678 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
|
| MipsAsmPrinter.cpp | 254 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
265 unsigned RegNum = TRI->getEncodingValue(Reg);
[all...] |
| MipsDelaySlotFiller.cpp | 72 RegDefsUses(const TargetRegisterInfo &TRI);
95 const TargetRegisterInfo &TRI;
295 RegDefsUses::RegDefsUses(const TargetRegisterInfo &TRI)
296 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {}
327 BitVector CallerSavedRegs(TRI.getNumRegs(), true);
332 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(MI.getParent()->getParent());
334 for (MCRegAliasIterator AI(*R, &TRI, true); AI.isValid(); ++AI
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ControlFlowFinalizer.cpp | 221 const R600RegisterInfo *TRI;
294 DstMI = TRI->getMatchingSuperReg(Reg,
295 TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)),
303 SrcMI = TRI->getMatchingSuperReg(Reg,
304 TRI->getSubRegFromChannel(TRI->getHWRegChan(Reg)),
472 : MachineFunctionPass(ID), TII(nullptr), TRI(nullptr), ST(nullptr) {}
478 TRI = static_cast<const R600RegisterInfo *>(ST->getRegisterInfo());
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