| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | [all...] |
| /external/llvm/ |
| CREDITS.TXT | 244 D: vreg subreg infrastructure, X86 codegen improvements based on subregs
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| /external/llvm/lib/CodeGen/ |
| LiveRangeCalc.h | 188 /// Creates subregister live ranges as needed if subreg liveness tracking is
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| TargetRegisterInfo.cpp | 294 /// \brief Check if the registers defined by the pair (RegisterClass, SubReg)
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| RegisterCoalescer.cpp | 345 // Both registers have subreg indices.
[all...] |
| MachineCSE.cpp | 152 // class given a super-reg class and subreg index.
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| StackMaps.cpp | 140 assert(!MOI->getSubReg() && "Physical subreg still around.");
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| MachineVerifier.cpp | [all...] |
| TailDuplication.cpp | 616 // demonstrated by test/CodeGen/Hexagon/tail-dup-subreg-abort.ll.
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/plugin/include/ |
| rtl.def | 366 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
370 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
372 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 596 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
622 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
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| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| X86InstrInfo.h | 193 /// true, then it's expected the pre-extension value is available as a subreg
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| X86RegisterInfo.td | 366 // that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
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| /prebuilts/go/darwin-x86/pkg/bootstrap/src/bootstrap/internal/obj/x86/ |
| asm6.go | 2858 func subreg(p *obj.Prog, from int, to int) { func
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/x86/ |
| asm6.go | 2855 func subreg(p *obj.Prog, from int, to int) { func
[all...] |
| /prebuilts/go/linux-x86/pkg/bootstrap/src/bootstrap/internal/obj/x86/ |
| asm6.go | 2858 func subreg(p *obj.Prog, from int, to int) { func
[all...] |
| /prebuilts/go/linux-x86/src/cmd/internal/obj/x86/ |
| asm6.go | 2855 func subreg(p *obj.Prog, from int, to int) { func
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | [all...] |
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 45 /// the list is modeled as <Reg:SubReg, SubIdx>.
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 525 bool ClearEven, unsigned SubReg) const;
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| /external/llvm/include/llvm/Target/ |
| Target.td | 394 bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg?
397 bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg?
[all...] |
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 374 // If subreg bit is set we're selecting the second produced newvalue
385 // Subreg bit should not be set for non-doublevector newvalue producers
[all...] |
