| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32.s | 9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips32r2.s | 9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips4.s | 9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips5.s | 9 bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| valid.s | 23 bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
24 bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| micromips-branch-relax.s | 97 bc1t test3
|
| micromips@mips4-fp.d | 17 [0-9a-f]+ <[^>]*> 43a4 fffe bc1t \$fcc1,0+000c <text_label\+0xc>
|
| mips4-fp.l | 4 .*:6: Error: opcode not supported on this processor: .* \(.*\) `bc1t \$fcc1,text_label'
|
| micromips@relax-at.d | 78 ([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
168 ([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
271 ([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
361 ([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
|
| micromips@relax.d | 78 ([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
168 ([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
271 ([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
361 ([0-9a-f]+) <[^>]*> 43a0 fffe bc1t \1 <.*>
|
| r6-removed.s | 13 bc1t 1f
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| select.ll | 323 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
355 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
451 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
522 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
554 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
650 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
|
| /art/compiler/utils/mips/ |
| assembler_mips.h | 217 void Bc1t(uint16_t imm16); // R2
218 void Bc1t(int cc, uint16_t imm16); // R2
382 void Bc1t(MipsLabel* label); // R2
383 void Bc1t(int cc, MipsLabel* label); // R2
[all...] |
| assembler_mips_test.cc | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrFPU.td | 516 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
557 def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
|
| MipsSEInstrInfo.cpp | 419 case Mips::BC1T: return Mips::BC1F;
420 case Mips::BC1F: return Mips::BC1T;
495 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
|
| /external/llvm/test/MC/Mips/ |
| micromips-fpu-instructions.s | 26 # CHECK-EL: bc1t 1332 # encoding: [0xa0,0x43,0x9a,0x02]
91 # CHECK-EB: bc1t 1332 # encoding: [0x43,0xa0,0x02,0x9a]
153 bc1t 1332
|
| /art/compiler/optimizing/ |
| code_generator_mips.cc | [all...] |
| /art/disassembler/ |
| disassembler_mips.cc | 224 { kITypeMask | (0x3e3 << 16), (17 << kOpcodeShift) | (8 << 21) | (1 << 16), "bc1t", "cB" },
456 case 'c': // Floating-point condition code flag in bc1f/bc1t and movf/movt.
|
| /external/llvm/test/MC/Disassembler/Mips/mips32/ |
| valid-mips32-el.txt | 17 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
18 0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| valid-mips32r2-el.txt | 18 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
19 0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| valid-mips32r3-el.txt | 15 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
16 0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| valid-mips32r5-el.txt | 15 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
16 0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| valid-mips4-el.txt | 20 0x01 0x00 0x01 0x45 # CHECK: bc1t 8
21 0x00 0x00 0x05 0x45 # CHECK: bc1t $fcc1, 4
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| valid-mips64r3-el.txt | 16 0x4c 0x01 0x01 0x45 # CHECK: bc1t 1332
17 0x4c 0x01 0x1d 0x45 # CHECK: bc1t $fcc7, 1332
|
