| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 53 cvt.l.d $f24,$f15
56 cvt.s.l $f15,$f30
57 cvt.s.w $f22,$f15
74 div.s $f4,$f5,$f15
162 neg.s $f1,$f15
236 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 57 cvt.l.d $f24,$f15
60 cvt.s.l $f15,$f30
61 cvt.s.w $f22,$f15
78 div.s $f4,$f5,$f15
184 neg.s $f1,$f15
265 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 57 cvt.l.d $f24,$f15
60 cvt.s.l $f15,$f30
61 cvt.s.w $f22,$f15
78 div.s $f4,$f5,$f15
185 neg.s $f1,$f15
267 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/SystemZ/ |
| insn-good-z196.s | 143 #CHECK: cdlfbr %f15, 0, %r0, 0 # encoding: [0xb3,0x91,0x00,0xf0]
150 cdlfbr %f15, 0, %r0, 0
157 #CHECK: cdlgbr %f15, 0, %r0, 0 # encoding: [0xb3,0xa1,0x00,0xf0]
164 cdlgbr %f15, 0, %r0, 0
171 #CHECK: celfbr %f15, 0, %r0, 0 # encoding: [0xb3,0x90,0x00,0xf0]
178 celfbr %f15, 0, %r0, 0
185 #CHECK: celgbr %f15, 0, %r0, 0 # encoding: [0xb3,0xa0,0x00,0xf0]
192 celgbr %f15, 0, %r0, 0
232 #CHECK: clfdbr %r0, 0, %f15, 0 # encoding: [0xb3,0x9d,0x00,0x0f]
239 clfdbr %r0, 0, %f15,
[all...] |
| /external/llvm/test/MC/Disassembler/Mips/mips3/ |
| valid-mips3-el.txt | 46 0x25 0x7e 0x20 0x46 # CHECK: cvt.l.d $f24, $f15
48 0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
50 0xa0 0x7d 0x80 0x46 # CHECK: cvt.s.w $f22, $f15
67 0x03 0x29 0x0f 0x46 # CHECK: div.s $f4, $f5, $f15
136 0x47 0x78 0x00 0x46 # CHECK: neg.s $f1, $f15
|
| valid-mips3.txt | 154 0x46 0x00 0x78 0x47 # CHECK: neg.s $f1, $f15
165 0x46 0x0f 0x29 0x03 # CHECK: div.s $f4, $f5, $f15
178 0x46 0x20 0x7e 0x25 # CHECK: cvt.l.d $f24, $f15
192 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
194 0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
|
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| valid-mips4-el.txt | 50 0x25 0x7e 0x20 0x46 # CHECK: cvt.l.d $f24, $f15
52 0xe0 0xf3 0xa0 0x46 # CHECK: cvt.s.l $f15, $f30
54 0xa0 0x7d 0x80 0x46 # CHECK: cvt.s.w $f22, $f15
71 0x03 0x29 0x0f 0x46 # CHECK: div.s $f4, $f5, $f15
153 0x47 0x78 0x00 0x46 # CHECK: neg.s $f1, $f15
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 56 cvt.l.d $f24,$f15
59 cvt.s.w $f22,$f15
67 div.s $f4,$f5,$f15
148 neg.s $f1,$f15
237 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| valid.s | 56 cvt.l.d $f24,$f15
59 cvt.s.w $f22,$f15
67 div.s $f4,$f5,$f15
148 neg.s $f1,$f15
237 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| valid.s | 56 cvt.l.d $f24,$f15
59 cvt.s.w $f22,$f15
67 div.s $f4,$f5,$f15
149 neg.s $f1,$f15
238 trunc.w.d $f22,$f15
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.td | 171 def F15 : Rf<15, "F15">, DwarfRegNum<[47]>;
197 def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[79]>;
|
| /external/llvm/test/MC/Disassembler/Mips/mips1/ |
| valid-mips1-el.txt | 36 0xa0 0x7d 0x80 0x46 # CHECK: cvt.s.w $f22, $f15
41 0x03 0x29 0x0f 0x46 # CHECK: div.s $f4, $f5, $f15
78 0x47 0x78 0x00 0x46 # CHECK: neg.s $f1, $f15
|
| valid-mips1.txt | 75 0x46 0x00 0x78 0x47 # CHECK: neg.s $f1, $f15
81 0x46 0x0f 0x29 0x03 # CHECK: div.s $f4, $f5, $f15
98 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
|
| /external/llvm/test/MC/Disassembler/Mips/mips2/ |
| valid-mips2-el.txt | 43 0xa0 0x7d 0x80 0x46 # CHECK: cvt.s.w $f22, $f15
48 0x03 0x29 0x0f 0x46 # CHECK: div.s $f4, $f5, $f15
92 0x47 0x78 0x00 0x46 # CHECK: neg.s $f1, $f15
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 15 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
71 trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 15 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
88 trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 15 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
86 trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/valgrind/coregrind/m_dispatch/ |
| dispatch-s390x-linux.S | 95 /* Save fprs: ABI: f8...f15 */
103 std %f15,160+56(SP)
162 ld %f15,160+56(SP)
|
| /external/valgrind/none/tests/ppc32/ |
| test_dfp2.c | 36 register double f15 __asm__ ("fr15");
475 f15 = d0x;
549 f15 = d0x;
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 59 cvt.l.d $f24,$f15
62 cvt.s.l $f15,$f30
63 cvt.s.w $f22,$f15
83 div.s $f4,$f5,$f15
201 neg.s $f1,$f15
286 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 59 cvt.l.d $f24,$f15
62 cvt.s.l $f15,$f30
63 cvt.s.w $f22,$f15
85 div.s $f4,$f5,$f15
217 neg.s $f1,$f15
312 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 59 cvt.l.d $f24,$f15
62 cvt.s.l $f15,$f30
63 cvt.s.w $f22,$f15
85 div.s $f4,$f5,$f15
217 neg.s $f1,$f15
312 trunc.w.d $f22,$f15
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 59 cvt.l.d $f24,$f15
62 cvt.s.l $f15,$f30
63 cvt.s.w $f22,$f15
85 div.s $f4,$f5,$f15
218 neg.s $f1,$f15
313 trunc.w.d $f22,$f15
|
| /external/clang/test/CodeGen/ |
| mips-clobber-reg.c | 100 __asm__ __volatile__ ("fadd.s $f15,77":::"$f15");
|
| /external/compiler-rt/lib/tsan/rtl/ |
| tsan_rtl_ppc64.S | 68 stfd f15,184(r3)
213 stfd f15,184(r3)
|
