1 //===-- SparcRegisterInfo.td - Sparc Register defs ---------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Declarations that describe the Sparc register file 12 //===----------------------------------------------------------------------===// 13 14 class SparcReg<bits<16> Enc, string n> : Register<n> { 15 let HWEncoding = Enc; 16 let Namespace = "SP"; 17 } 18 19 class SparcCtrlReg<bits<16> Enc, string n>: Register<n> { 20 let HWEncoding = Enc; 21 let Namespace = "SP"; 22 } 23 24 let Namespace = "SP" in { 25 def sub_even : SubRegIndex<32>; 26 def sub_odd : SubRegIndex<32, 32>; 27 def sub_even64 : SubRegIndex<64>; 28 def sub_odd64 : SubRegIndex<64, 64>; 29 } 30 31 // Registers are identified with 5-bit ID numbers. 32 // Ri - 32-bit integer registers 33 class Ri<bits<16> Enc, string n> : SparcReg<Enc, n>; 34 35 // Rdi - pairs of 32-bit integer registers 36 class Rdi<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> { 37 let SubRegs = subregs; 38 let SubRegIndices = [sub_even, sub_odd]; 39 let CoveredBySubRegs = 1; 40 } 41 // Rf - 32-bit floating-point registers 42 class Rf<bits<16> Enc, string n> : SparcReg<Enc, n>; 43 44 // Rd - Slots in the FP register file for 64-bit floating-point values. 45 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> { 46 let SubRegs = subregs; 47 let SubRegIndices = [sub_even, sub_odd]; 48 let CoveredBySubRegs = 1; 49 } 50 51 // Rq - Slots in the FP register file for 128-bit floating-point values. 52 class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> { 53 let SubRegs = subregs; 54 let SubRegIndices = [sub_even64, sub_odd64]; 55 let CoveredBySubRegs = 1; 56 } 57 58 // Control Registers 59 def ICC : SparcCtrlReg<0, "ICC">; // This represents icc and xcc in 64-bit code. 60 foreach I = 0-3 in 61 def FCC#I : SparcCtrlReg<I, "FCC"#I>; 62 63 def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register. 64 65 // Y register 66 def Y : SparcCtrlReg<0, "Y">, DwarfRegNum<[64]>; 67 // Ancillary state registers (implementation defined) 68 def ASR1 : SparcCtrlReg<1, "ASR1">; 69 def ASR2 : SparcCtrlReg<2, "ASR2">; 70 def ASR3 : SparcCtrlReg<3, "ASR3">; 71 def ASR4 : SparcCtrlReg<4, "ASR4">; 72 def ASR5 : SparcCtrlReg<5, "ASR5">; 73 def ASR6 : SparcCtrlReg<6, "ASR6">; 74 def ASR7 : SparcCtrlReg<7, "ASR7">; 75 def ASR8 : SparcCtrlReg<8, "ASR8">; 76 def ASR9 : SparcCtrlReg<9, "ASR9">; 77 def ASR10 : SparcCtrlReg<10, "ASR10">; 78 def ASR11 : SparcCtrlReg<11, "ASR11">; 79 def ASR12 : SparcCtrlReg<12, "ASR12">; 80 def ASR13 : SparcCtrlReg<13, "ASR13">; 81 def ASR14 : SparcCtrlReg<14, "ASR14">; 82 def ASR15 : SparcCtrlReg<15, "ASR15">; 83 def ASR16 : SparcCtrlReg<16, "ASR16">; 84 def ASR17 : SparcCtrlReg<17, "ASR17">; 85 def ASR18 : SparcCtrlReg<18, "ASR18">; 86 def ASR19 : SparcCtrlReg<19, "ASR19">; 87 def ASR20 : SparcCtrlReg<20, "ASR20">; 88 def ASR21 : SparcCtrlReg<21, "ASR21">; 89 def ASR22 : SparcCtrlReg<22, "ASR22">; 90 def ASR23 : SparcCtrlReg<23, "ASR23">; 91 def ASR24 : SparcCtrlReg<24, "ASR24">; 92 def ASR25 : SparcCtrlReg<25, "ASR25">; 93 def ASR26 : SparcCtrlReg<26, "ASR26">; 94 def ASR27 : SparcCtrlReg<27, "ASR27">; 95 def ASR28 : SparcCtrlReg<28, "ASR28">; 96 def ASR29 : SparcCtrlReg<29, "ASR29">; 97 def ASR30 : SparcCtrlReg<30, "ASR30">; 98 def ASR31 : SparcCtrlReg<31, "ASR31">; 99 100 // Note that PSR, WIM, and TBR don't exist on the SparcV9, only the V8. 101 def PSR : SparcCtrlReg<0, "PSR">; 102 def WIM : SparcCtrlReg<0, "WIM">; 103 def TBR : SparcCtrlReg<0, "TBR">; 104 105 def TPC : SparcCtrlReg<0, "TPC">; 106 def TNPC : SparcCtrlReg<1, "TNPC">; 107 def TSTATE : SparcCtrlReg<2, "TSTATE">; 108 def TT : SparcCtrlReg<3, "TT">; 109 def TICK : SparcCtrlReg<4, "TICK">; 110 def TBA : SparcCtrlReg<5, "TBA">; 111 def PSTATE : SparcCtrlReg<6, "PSTATE">; 112 def TL : SparcCtrlReg<7, "TL">; 113 def PIL : SparcCtrlReg<8, "PIL">; 114 def CWP : SparcCtrlReg<9, "CWP">; 115 def CANSAVE : SparcCtrlReg<10, "CANSAVE">; 116 def CANRESTORE : SparcCtrlReg<11, "CANRESTORE">; 117 def CLEANWIN : SparcCtrlReg<12, "CLEANWIN">; 118 def OTHERWIN : SparcCtrlReg<13, "OTHERWIN">; 119 def WSTATE : SparcCtrlReg<14, "WSTATE">; 120 121 // Integer registers 122 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>; 123 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>; 124 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>; 125 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>; 126 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>; 127 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>; 128 def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>; 129 def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>; 130 def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>; 131 def O1 : Ri< 9, "O1">, DwarfRegNum<[9]>; 132 def O2 : Ri<10, "O2">, DwarfRegNum<[10]>; 133 def O3 : Ri<11, "O3">, DwarfRegNum<[11]>; 134 def O4 : Ri<12, "O4">, DwarfRegNum<[12]>; 135 def O5 : Ri<13, "O5">, DwarfRegNum<[13]>; 136 def O6 : Ri<14, "SP">, DwarfRegNum<[14]>; 137 def O7 : Ri<15, "O7">, DwarfRegNum<[15]>; 138 def L0 : Ri<16, "L0">, DwarfRegNum<[16]>; 139 def L1 : Ri<17, "L1">, DwarfRegNum<[17]>; 140 def L2 : Ri<18, "L2">, DwarfRegNum<[18]>; 141 def L3 : Ri<19, "L3">, DwarfRegNum<[19]>; 142 def L4 : Ri<20, "L4">, DwarfRegNum<[20]>; 143 def L5 : Ri<21, "L5">, DwarfRegNum<[21]>; 144 def L6 : Ri<22, "L6">, DwarfRegNum<[22]>; 145 def L7 : Ri<23, "L7">, DwarfRegNum<[23]>; 146 def I0 : Ri<24, "I0">, DwarfRegNum<[24]>; 147 def I1 : Ri<25, "I1">, DwarfRegNum<[25]>; 148 def I2 : Ri<26, "I2">, DwarfRegNum<[26]>; 149 def I3 : Ri<27, "I3">, DwarfRegNum<[27]>; 150 def I4 : Ri<28, "I4">, DwarfRegNum<[28]>; 151 def I5 : Ri<29, "I5">, DwarfRegNum<[29]>; 152 def I6 : Ri<30, "FP">, DwarfRegNum<[30]>; 153 def I7 : Ri<31, "I7">, DwarfRegNum<[31]>; 154 155 // Floating-point registers 156 def F0 : Rf< 0, "F0">, DwarfRegNum<[32]>; 157 def F1 : Rf< 1, "F1">, DwarfRegNum<[33]>; 158 def F2 : Rf< 2, "F2">, DwarfRegNum<[34]>; 159 def F3 : Rf< 3, "F3">, DwarfRegNum<[35]>; 160 def F4 : Rf< 4, "F4">, DwarfRegNum<[36]>; 161 def F5 : Rf< 5, "F5">, DwarfRegNum<[37]>; 162 def F6 : Rf< 6, "F6">, DwarfRegNum<[38]>; 163 def F7 : Rf< 7, "F7">, DwarfRegNum<[39]>; 164 def F8 : Rf< 8, "F8">, DwarfRegNum<[40]>; 165 def F9 : Rf< 9, "F9">, DwarfRegNum<[41]>; 166 def F10 : Rf<10, "F10">, DwarfRegNum<[42]>; 167 def F11 : Rf<11, "F11">, DwarfRegNum<[43]>; 168 def F12 : Rf<12, "F12">, DwarfRegNum<[44]>; 169 def F13 : Rf<13, "F13">, DwarfRegNum<[45]>; 170 def F14 : Rf<14, "F14">, DwarfRegNum<[46]>; 171 def F15 : Rf<15, "F15">, DwarfRegNum<[47]>; 172 def F16 : Rf<16, "F16">, DwarfRegNum<[48]>; 173 def F17 : Rf<17, "F17">, DwarfRegNum<[49]>; 174 def F18 : Rf<18, "F18">, DwarfRegNum<[50]>; 175 def F19 : Rf<19, "F19">, DwarfRegNum<[51]>; 176 def F20 : Rf<20, "F20">, DwarfRegNum<[52]>; 177 def F21 : Rf<21, "F21">, DwarfRegNum<[53]>; 178 def F22 : Rf<22, "F22">, DwarfRegNum<[54]>; 179 def F23 : Rf<23, "F23">, DwarfRegNum<[55]>; 180 def F24 : Rf<24, "F24">, DwarfRegNum<[56]>; 181 def F25 : Rf<25, "F25">, DwarfRegNum<[57]>; 182 def F26 : Rf<26, "F26">, DwarfRegNum<[58]>; 183 def F27 : Rf<27, "F27">, DwarfRegNum<[59]>; 184 def F28 : Rf<28, "F28">, DwarfRegNum<[60]>; 185 def F29 : Rf<29, "F29">, DwarfRegNum<[61]>; 186 def F30 : Rf<30, "F30">, DwarfRegNum<[62]>; 187 def F31 : Rf<31, "F31">, DwarfRegNum<[63]>; 188 189 // Aliases of the F* registers used to hold 64-bit fp values (doubles) 190 def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[72]>; 191 def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[73]>; 192 def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[74]>; 193 def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[75]>; 194 def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[76]>; 195 def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[77]>; 196 def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[78]>; 197 def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[79]>; 198 def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[80]>; 199 def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[81]>; 200 def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[82]>; 201 def D11 : Rd<22, "F22", [F22, F23]>, DwarfRegNum<[83]>; 202 def D12 : Rd<24, "F24", [F24, F25]>, DwarfRegNum<[84]>; 203 def D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<[85]>; 204 def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<[86]>; 205 def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[87]>; 206 207 // Unaliased double precision floating point registers. 208 // FIXME: Define DwarfRegNum for these registers. 209 def D16 : SparcReg< 1, "F32">; 210 def D17 : SparcReg< 3, "F34">; 211 def D18 : SparcReg< 5, "F36">; 212 def D19 : SparcReg< 7, "F38">; 213 def D20 : SparcReg< 9, "F40">; 214 def D21 : SparcReg<11, "F42">; 215 def D22 : SparcReg<13, "F44">; 216 def D23 : SparcReg<15, "F46">; 217 def D24 : SparcReg<17, "F48">; 218 def D25 : SparcReg<19, "F50">; 219 def D26 : SparcReg<21, "F52">; 220 def D27 : SparcReg<23, "F54">; 221 def D28 : SparcReg<25, "F56">; 222 def D29 : SparcReg<27, "F58">; 223 def D30 : SparcReg<29, "F60">; 224 def D31 : SparcReg<31, "F62">; 225 226 // Aliases of the F* registers used to hold 128-bit for values (long doubles). 227 def Q0 : Rq< 0, "F0", [D0, D1]>; 228 def Q1 : Rq< 4, "F4", [D2, D3]>; 229 def Q2 : Rq< 8, "F8", [D4, D5]>; 230 def Q3 : Rq<12, "F12", [D6, D7]>; 231 def Q4 : Rq<16, "F16", [D8, D9]>; 232 def Q5 : Rq<20, "F20", [D10, D11]>; 233 def Q6 : Rq<24, "F24", [D12, D13]>; 234 def Q7 : Rq<28, "F28", [D14, D15]>; 235 def Q8 : Rq< 1, "F32", [D16, D17]>; 236 def Q9 : Rq< 5, "F36", [D18, D19]>; 237 def Q10 : Rq< 9, "F40", [D20, D21]>; 238 def Q11 : Rq<13, "F44", [D22, D23]>; 239 def Q12 : Rq<17, "F48", [D24, D25]>; 240 def Q13 : Rq<21, "F52", [D26, D27]>; 241 def Q14 : Rq<25, "F56", [D28, D29]>; 242 def Q15 : Rq<29, "F60", [D30, D31]>; 243 244 // Aliases of the integer registers used for LDD/STD double-word operations 245 def G0_G1 : Rdi<0, "G0", [G0, G1]>; 246 def G2_G3 : Rdi<2, "G2", [G2, G3]>; 247 def G4_G5 : Rdi<4, "G4", [G4, G5]>; 248 def G6_G7 : Rdi<6, "G6", [G6, G7]>; 249 def O0_O1 : Rdi<8, "O0", [O0, O1]>; 250 def O2_O3 : Rdi<10, "O2", [O2, O3]>; 251 def O4_O5 : Rdi<12, "O4", [O4, O5]>; 252 def O6_O7 : Rdi<14, "O6", [O6, O7]>; 253 def L0_L1 : Rdi<16, "L0", [L0, L1]>; 254 def L2_L3 : Rdi<18, "L2", [L2, L3]>; 255 def L4_L5 : Rdi<20, "L4", [L4, L5]>; 256 def L6_L7 : Rdi<22, "L6", [L6, L7]>; 257 def I0_I1 : Rdi<24, "I0", [I0, I1]>; 258 def I2_I3 : Rdi<26, "I2", [I2, I3]>; 259 def I4_I5 : Rdi<28, "I4", [I4, I5]>; 260 def I6_I7 : Rdi<30, "I6", [I6, I7]>; 261 262 // Register classes. 263 // 264 // FIXME: the register order should be defined in terms of the preferred 265 // allocation order... 266 // 267 // This register class should not be used to hold i64 values, use the I64Regs 268 // register class for that. The i64 type is included here to allow i64 patterns 269 // using the integer instructions. 270 def IntRegs : RegisterClass<"SP", [i32, i64], 32, 271 (add (sequence "I%u", 0, 7), 272 (sequence "G%u", 0, 7), 273 (sequence "L%u", 0, 7), 274 (sequence "O%u", 0, 7))>; 275 276 // Should be in the same order as IntRegs. 277 def IntPair : RegisterClass<"SP", [v2i32], 64, 278 (add I0_I1, I2_I3, I4_I5, I6_I7, 279 G0_G1, G2_G3, G4_G5, G6_G7, 280 L0_L1, L2_L3, L4_L5, L6_L7, 281 O0_O1, O2_O3, O4_O5, O6_O7)>; 282 283 // Register class for 64-bit mode, with a 64-bit spill slot size. 284 // These are the same as the 32-bit registers, so TableGen will consider this 285 // to be a sub-class of IntRegs. That works out because requiring a 64-bit 286 // spill slot is a stricter constraint than only requiring a 32-bit spill slot. 287 def I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>; 288 289 // Floating point register classes. 290 def FPRegs : RegisterClass<"SP", [f32], 32, (sequence "F%u", 0, 31)>; 291 292 def DFPRegs : RegisterClass<"SP", [f64], 64, (sequence "D%u", 0, 31)>; 293 294 def QFPRegs : RegisterClass<"SP", [f128], 128, (sequence "Q%u", 0, 15)>; 295 296 // Floating point control register classes. 297 def FCCRegs : RegisterClass<"SP", [i1], 1, (sequence "FCC%u", 0, 3)>; 298 299 // Ancillary state registers 300 def ASRRegs : RegisterClass<"SP", [i32], 32, 301 (add Y, (sequence "ASR%u", 1, 31))> { 302 let isAllocatable = 0; 303 } 304 305 // Privileged Registers 306 def PRRegs : RegisterClass<"SP", [i64], 64, 307 (add TPC, TNPC, TSTATE, TT, TICK, TBA, PSTATE, TL, PIL, CWP, 308 CANSAVE, CANRESTORE, CLEANWIN, OTHERWIN, WSTATE)>; 309
