| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i860/ |
| fldst07.d | 25 3c: 0a ff b3 65 pfld.l -248\(%r13\),%f19
57 bc: 02 e0 b3 61 pfld.l %r28\(%r13\),%f19
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/score/ |
| rD_rA_BN.d | 58 6c: 6f19 slli! r15, 3
59 6e: 6f19 slli! r15, 3
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.td | 175 def F19 : Rf<19, "F19">, DwarfRegNum<[51]>;
199 def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[81]>;
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips5.s | 52 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
77 swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
90 swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/clang/test/CodeGen/ |
| mips-clobber-reg.c | 104 __asm__ __volatile__ ("fadd.s $f19,77":::"$f19");
|
| /external/compiler-rt/lib/tsan/rtl/ |
| tsan_rtl_ppc64.S | 76 stfd f19,216(r3)
221 stfd f19,216(r3)
|
| /external/libjpeg-turbo/simd/ |
| jsimd_mips_dspr2_asm.h | 78 #define f19 $f19 macro
|
| /external/llvm/test/CodeGen/Mips/cconv/ |
| callee-saved-float.ll | 26 call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f13},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
50 ; ALL-INV-NOT: sdc1 $f19,
|
| /external/llvm/test/CodeGen/SystemZ/ |
| fp-libcall.ll | 131 define float @f19(float %x) {
132 ; CHECK-LABEL: f19:
|
| int-cmp-09.ll | 214 define double @f19(double %a, double %b, i32 %i1) {
215 ; CHECK-LABEL: f19:
|
| int-cmp-15.ll | 229 define double @f19(double %a, double %b, i64 %base, i64 %index) {
230 ; CHECK-LABEL: f19:
|
| int-const-02.ll | 157 define i64 @f19() {
158 ; CHECK-LABEL: f19:
|
| rnsbg-01.ll | 206 define i64 @f19(i64 %a, i64 %b, i64 *%dest) {
207 ; CHECK-LABEL: f19:
|
| vec-const-07.ll | 210 define <16 x i8> @f19() {
211 ; CHECK-LABEL: f19:
|
| vec-move-05.ll | 172 define float @f19(<4 x float> %val) {
173 ; CHECK-LABEL: f19:
|
| vec-perm-03.ll | 240 define <16 x i8> @f19(i8 *%base, i64 %index) {
241 ; CHECK-LABEL: f19:
|
| /external/valgrind/none/tests/mips32/ |
| MoveIns.c | 302 TESTINSNMOVE("mfc1 $a2, $f19", 8, f19, a2);
331 TESTINSNMOVEt("mtc1 $a2, $f19", 10, f19, a2);
360 TESTINSNMOVE1s("mov.s $f18, $f19", 8, f18, f19);
361 TESTINSNMOVE1s("mov.s $f19, $f20", 12, f19, f20);
|
| /prebuilts/go/darwin-x86/src/cmd/asm/internal/asm/ |
| operand_test.go | 330 {"F19", "F19"},
|
| /prebuilts/go/linux-x86/src/cmd/asm/internal/asm/ |
| operand_test.go | 330 {"F19", "F19"},
|
| /art/compiler/jni/quick/mips64/ |
| calling_convention_mips64.cc | 31 F12, F13, F14, F15, F16, F17, F18, F19
|
| /external/llvm/test/CodeGen/ARM/ |
| aapcs-hfa.ll | 146 define void @f19({ <2 x i64>, <4 x i32> } %a) {
|
| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips4.s | 30 swxc1 $f19,$12($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64r2.s | 17 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/mesa3d/src/mesa/sparc/ |
| sparc_matrix.h | 38 #define M3 %f19
|
| /external/v8/src/mips/ |
| constants-mips.cc | 82 "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21",
|
