| /external/llvm/test/MC/Mips/mips3/ |
| invalid-mips5.s | 13 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
22 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
24 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
25 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/CodeGen/Mips/ |
| fcmp.ll | 30 ; 32-C: movf $2, $zero, $fcc0
34 ; 64-C: movf $2, $zero, $fcc0
54 ; 32-C: movt $2, $zero, $fcc0
58 ; 64-C: movt $2, $zero, $fcc0
78 ; 32-C: movt $2, $zero, $fcc0
82 ; 64-C: movt $2, $zero, $fcc0
102 ; 32-C: movf $2, $zero, $fcc0
106 ; 64-C: movf $2, $zero, $fcc0
126 ; 32-C: movf $2, $zero, $fcc0
130 ; 64-C: movf $2, $zero, $fcc0
[all...] |
| select.ll | 207 ; 32: movt.s $f14, $f12, $fcc0
213 ; 32R2: movt.s $f14, $f12, $fcc0
222 ; 64: movt.s $f13, $f12, $fcc0
226 ; 64R2: movt.s $f13, $f12, $fcc0
244 ; 32: movt.s $f14, $f12, $fcc0
250 ; 32R2: movt.s $f14, $f12, $fcc0
259 ; 64: movt.s $f13, $f12, $fcc0
263 ; 64R2: movt.s $f13, $f12, $fcc0
281 ; 32: movf.s $f14, $f12, $fcc0
287 ; 32R2: movf.s $f14, $f12, $fcc0
[all...] |
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| fpcmpa.ll | 26 ; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
47 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
67 ; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
88 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
108 ; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
128 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
148 ; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
168 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
188 ; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
208 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| micromips@mips4-fp.d | 27 [0-9a-f]+ <[^>]*> 5486 0220 movf\.d \$f4,\$f6,\$fcc0
28 [0-9a-f]+ <[^>]*> 5486 0020 movf\.s \$f4,\$f6,\$fcc0
32 [0-9a-f]+ <[^>]*> 5486 0260 movt\.d \$f4,\$f6,\$fcc0
33 [0-9a-f]+ <[^>]*> 5486 0060 movt\.s \$f4,\$f6,\$fcc0
|
| mips4-fp.l | 12 .*:15: Error: opcode not supported on this processor: .* \(.*\) `movf.d \$f4,\$f6,\$fcc0'
13 .*:16: Error: opcode not supported on this processor: .* \(.*\) `movf.s \$f4,\$f6,\$fcc0'
17 .*:20: Error: opcode not supported on this processor: .* \(.*\) `movt.d \$f4,\$f6,\$fcc0'
18 .*:21: Error: opcode not supported on this processor: .* \(.*\) `movt.s \$f4,\$f6,\$fcc0'
|
| r6-removed.s | 146 movf $8,$9,$fcc0
147 movf.s $f8,$f9,$fcc0
148 movf.d $f8,$f10,$fcc0
149 movf.ps $f8,$f10,$fcc0
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| select.ll | 332 ; CMOV-32: movt.s $f14, $f12, $fcc0
339 ; CMOV-64: movt.s $f13, $f12, $fcc0
364 ; CMOV-32: movt.s $f14, $f12, $fcc0
371 ; CMOV-64: movt.s $f13, $f12, $fcc0
396 ; CMOV-32: movf.s $f14, $f12, $fcc0
403 ; CMOV-64: movf.s $f13, $f12, $fcc0
428 ; CMOV-32: movf.s $f14, $f12, $fcc0
435 ; CMOV-64: movf.s $f13, $f12, $fcc0
460 ; CMOV-32: movt.s $f14, $f12, $fcc0
467 ; CMOV-64: movt.s $f13, $f12, $fcc0
[all...] |
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32r2.s | 31 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
33 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
35 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
40 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
42 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
43 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 51 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
53 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
55 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
60 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
62 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
63 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 50 movf $gp,$a0,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
52 movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
54 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
59 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
61 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
62 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| valid.s | 19 bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
21 bc1fl $fcc0,50 # CHECK: bc1fl 50 # encoding: [0x45,0x02,0x00,0x0c]
23 bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
25 bc1tl $fcc0,-8239 # CHECK: bc1tl -8239 # encoding: [0x45,0x03,0xf7,0xf4]
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrAliases.td | 206 // fb<cond> %fcc0, $imm
211 // fb<cond>,pt %fcc0, $imm
216 // fb<cond>,a %fcc0, $imm
221 // fb<cond>,a,pt %fcc0, $imm
226 // fb<cond>,pn %fcc0, $imm
231 // fb<cond>,a,pn %fcc0, $imm
240 // fmovq<cond> %fcc0, $rs2, $rd
445 def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
446 def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
447 def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>
[all...] |
| /external/valgrind/none/tests/mips64/ |
| move_instructions.stdout.exp-BE | [all...] |
| move_instructions.stdout.exp-LE | [all...] |
| /external/llvm/test/MC/Mips/ |
| mips-jump-delay-slots.s | 55 bc1fl $fcc0, 1332
64 bc1tl $fcc0, 1332
|
| micromips-fpu-instructions.s | 62 # CHECK-EL: movt.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x00]
63 # CHECK-EL: movt.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x02]
64 # CHECK-EL: movf.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x00]
65 # CHECK-EL: movf.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x02]
127 # CHECK-EB: movt.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x60]
128 # CHECK-EB: movt.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x60]
129 # CHECK-EB: movf.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x20]
130 # CHECK-EB: movf.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x20]
188 movt.s $f4, $f6, $fcc0
189 movt.d $f4, $f6, $fcc0
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sparc/ |
| hpcvis3.s | 75 flcmps %fcc0, %f1, %f3
79 flcmpd %fcc0, %f12, %f14
|
| /external/llvm/test/CodeGen/SPARC/ |
| 2011-01-11-CC.ll | 75 ;V9: mov{{e|ne}} %fcc0
90 ;V9: fmovs{{e|ne}} %fcc0
106 ;V9: fmovd{{e|ne}} %fcc0
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips4.s | 55 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
57 movf.d $f6,$f10,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
59 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
64 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
66 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
67 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 54 movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
56 movf.d $f6,$f10,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
58 movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
63 movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
65 movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
66 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/lib/Target/Sparc/InstPrinter/ |
| SparcInstPrinter.cpp | 87 || (MI->getOperand(0).getReg() != SP::FCC0))
89 // if V8, skip printing %fcc0.
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips2.s | 9 bc1fl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 bc1tl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips2.s | 9 bc1fl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 bc1tl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 315 // bc1t $fcc0, $L1 => bc1t $L1
316 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS);
318 // bc1f $fcc0, $L1 => bc1f $L1
319 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1f", MI, 1, OS);
|
