1 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ 2 ; RUN: < %s | FileCheck %s 3 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ 4 ; RUN: < %s | FileCheck %s 5 6 @f1 = common global float 0.000000e+00, align 4 7 @f2 = common global float 0.000000e+00, align 4 8 @b1 = common global i32 0, align 4 9 @d1 = common global double 0.000000e+00, align 8 10 @d2 = common global double 0.000000e+00, align 8 11 12 ; Function Attrs: nounwind 13 define void @feq1() { 14 entry: 15 %0 = load float, float* @f1, align 4 16 %1 = load float, float* @f2, align 4 17 %cmp = fcmp oeq float %0, %1 18 ; CHECK-LABEL: feq1: 19 ; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) 20 ; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) 21 ; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) 22 ; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) 23 ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 24 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 25 ; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]] 26 ; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 27 28 %conv = zext i1 %cmp to i32 29 store i32 %conv, i32* @b1, align 4 30 ret void 31 } 32 33 ; Function Attrs: nounwind 34 define void @fne1() { 35 entry: 36 %0 = load float, float* @f1, align 4 37 %1 = load float, float* @f2, align 4 38 %cmp = fcmp une float %0, %1 39 ; CHECK-LABEL: fne1: 40 ; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) 41 ; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) 42 ; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) 43 ; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) 44 ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 45 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 46 ; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]] 47 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 48 %conv = zext i1 %cmp to i32 49 store i32 %conv, i32* @b1, align 4 50 ret void 51 } 52 53 ; Function Attrs: nounwind 54 define void @flt1() { 55 entry: 56 %0 = load float, float* @f1, align 4 57 %1 = load float, float* @f2, align 4 58 %cmp = fcmp olt float %0, %1 59 ; CHECK-LABEL: flt1: 60 ; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) 61 ; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) 62 ; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) 63 ; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) 64 ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 65 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 66 ; CHECK: c.olt.s $f[[REG_F1]], $f[[REG_F2]] 67 ; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 68 69 %conv = zext i1 %cmp to i32 70 store i32 %conv, i32* @b1, align 4 71 ret void 72 } 73 74 ; Function Attrs: nounwind 75 define void @fgt1() { 76 entry: 77 %0 = load float, float* @f1, align 4 78 %1 = load float, float* @f2, align 4 79 %cmp = fcmp ogt float %0, %1 80 ; CHECK-LABEL: fgt1: 81 ; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) 82 ; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) 83 ; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) 84 ; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) 85 ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 86 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 87 ; CHECK: c.ule.s $f[[REG_F1]], $f[[REG_F2]] 88 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 89 %conv = zext i1 %cmp to i32 90 store i32 %conv, i32* @b1, align 4 91 ret void 92 } 93 94 ; Function Attrs: nounwind 95 define void @fle1() { 96 entry: 97 %0 = load float, float* @f1, align 4 98 %1 = load float, float* @f2, align 4 99 %cmp = fcmp ole float %0, %1 100 ; CHECK-LABEL: fle1: 101 ; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) 102 ; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) 103 ; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) 104 ; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) 105 ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 106 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 107 ; CHECK: c.ole.s $f[[REG_F1]], $f[[REG_F2]] 108 ; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 109 %conv = zext i1 %cmp to i32 110 store i32 %conv, i32* @b1, align 4 111 ret void 112 } 113 114 ; Function Attrs: nounwind 115 define void @fge1() { 116 entry: 117 %0 = load float, float* @f1, align 4 118 %1 = load float, float* @f2, align 4 119 %cmp = fcmp oge float %0, %1 120 ; CHECK-LABEL: fge1: 121 ; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}}) 122 ; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}}) 123 ; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]]) 124 ; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]]) 125 ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 126 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 127 ; CHECK: c.ult.s $f[[REG_F1]], $f[[REG_F2]] 128 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 129 %conv = zext i1 %cmp to i32 130 store i32 %conv, i32* @b1, align 4 131 ret void 132 } 133 134 ; Function Attrs: nounwind 135 define void @deq1() { 136 entry: 137 %0 = load double, double* @d1, align 8 138 %1 = load double, double* @d2, align 8 139 %cmp = fcmp oeq double %0, %1 140 ; CHECK-LABEL: deq1: 141 ; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) 142 ; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) 143 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) 144 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) 145 ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 146 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 147 ; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]] 148 ; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 149 %conv = zext i1 %cmp to i32 150 store i32 %conv, i32* @b1, align 4 151 ret void 152 } 153 154 ; Function Attrs: nounwind 155 define void @dne1() { 156 entry: 157 %0 = load double, double* @d1, align 8 158 %1 = load double, double* @d2, align 8 159 %cmp = fcmp une double %0, %1 160 ; CHECK-LABEL: dne1: 161 ; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) 162 ; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) 163 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) 164 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) 165 ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 166 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 167 ; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]] 168 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 169 %conv = zext i1 %cmp to i32 170 store i32 %conv, i32* @b1, align 4 171 ret void 172 } 173 174 ; Function Attrs: nounwind 175 define void @dlt1() { 176 entry: 177 %0 = load double, double* @d1, align 8 178 %1 = load double, double* @d2, align 8 179 %cmp = fcmp olt double %0, %1 180 ; CHECK-LABEL: dlt1: 181 ; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) 182 ; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) 183 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) 184 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) 185 ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 186 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 187 ; CHECK: c.olt.d $f[[REG_D1]], $f[[REG_D2]] 188 ; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 189 %conv = zext i1 %cmp to i32 190 store i32 %conv, i32* @b1, align 4 191 ret void 192 } 193 194 ; Function Attrs: nounwind 195 define void @dgt1() { 196 entry: 197 %0 = load double, double* @d1, align 8 198 %1 = load double, double* @d2, align 8 199 %cmp = fcmp ogt double %0, %1 200 ; CHECK-LABEL: dgt1: 201 ; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) 202 ; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) 203 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) 204 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) 205 ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 206 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 207 ; CHECK: c.ule.d $f[[REG_D1]], $f[[REG_D2]] 208 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 209 %conv = zext i1 %cmp to i32 210 store i32 %conv, i32* @b1, align 4 211 ret void 212 } 213 214 ; Function Attrs: nounwind 215 define void @dle1() { 216 entry: 217 %0 = load double, double* @d1, align 8 218 %1 = load double, double* @d2, align 8 219 %cmp = fcmp ole double %0, %1 220 ; CHECK-LABEL: dle1: 221 ; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) 222 ; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) 223 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) 224 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) 225 ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 226 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 227 ; CHECK: c.ole.d $f[[REG_D1]], $f[[REG_D2]] 228 ; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0 229 %conv = zext i1 %cmp to i32 230 store i32 %conv, i32* @b1, align 4 231 ret void 232 } 233 234 ; Function Attrs: nounwind 235 define void @dge1() { 236 entry: 237 %0 = load double, double* @d1, align 8 238 %1 = load double, double* @d2, align 8 239 %cmp = fcmp oge double %0, %1 240 ; CHECK-LABEL: dge1: 241 ; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}}) 242 ; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}}) 243 ; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]]) 244 ; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]]) 245 ; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0 246 ; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1 247 ; CHECK: c.ult.d $f[[REG_D1]], $f[[REG_D2]] 248 ; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0 249 %conv = zext i1 %cmp to i32 250 store i32 %conv, i32* @b1, align 4 251 ret void 252 } 253 254 255
