| /external/valgrind/auxprogs/ |
| ppcfround.c | 209 INSN(fmul, "fmul %%f4, %%f1,%%f2");
210 INSN(fmul_, "fmul. %%f4, %%f1,%%f2");
463 do_N_binary("fmul", insn_fmul, args, nargs, SHOW_ALL);
|
| /external/valgrind/none/tests/amd64/ |
| insn_fpu.def | 275 fmul st0.ps[1234.5678] st2.ps[8765.4321] => st2.ps[10821520.2237464]
276 fmul st0.ps[-1234.5678] st2.ps[8765.4321] => st2.ps[-10821520.2237464]
277 fmul st0.ps[1234.5678] st2.ps[-8765.4321] => st2.ps[-10821520.2237464]
278 fmul st0.ps[-1234.5678] st2.ps[-8765.4321] => st2.ps[10821520.2237464]
279 fmul st0.pd[1234567.7654321] st2.pd[7654321.1234567] => st2.pd[9449778125285.66]
280 fmul st0.pd[-1234567.7654321] st2.pd[7654321.1234567] => st2.pd[-9449778125285.66]
281 fmul st0.pd[1234567.7654321] st2.pd[-7654321.1234567] => st2.pd[-9449778125285.66]
282 fmul st0.pd[-1234567.7654321] st2.pd[-7654321.1234567] => st2.pd[9449778125285.66]
283 fmul st2.ps[1234.5678] st0.ps[8765.4321] => st0.ps[10821520.2237464]
284 fmul st2.ps[-1234.5678] st0.ps[8765.4321] => st0.ps[-10821520.2237464
[all...] |
| /external/valgrind/none/tests/x86/ |
| insn_fpu.def | 275 fmul st0.ps[1234.5678] st2.ps[8765.4321] => st2.ps[10821520.2237464]
276 fmul st0.ps[-1234.5678] st2.ps[8765.4321] => st2.ps[-10821520.2237464]
277 fmul st0.ps[1234.5678] st2.ps[-8765.4321] => st2.ps[-10821520.2237464]
278 fmul st0.ps[-1234.5678] st2.ps[-8765.4321] => st2.ps[10821520.2237464]
279 fmul st0.pd[1234567.7654321] st2.pd[7654321.1234567] => st2.pd[9449778125285.66]
280 fmul st0.pd[-1234567.7654321] st2.pd[7654321.1234567] => st2.pd[-9449778125285.66]
281 fmul st0.pd[1234567.7654321] st2.pd[-7654321.1234567] => st2.pd[-9449778125285.66]
282 fmul st0.pd[-1234567.7654321] st2.pd[-7654321.1234567] => st2.pd[9449778125285.66]
283 fmul st2.ps[1234.5678] st0.ps[8765.4321] => st0.ps[10821520.2237464]
284 fmul st2.ps[-1234.5678] st0.ps[8765.4321] => st0.ps[-10821520.2237464
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/pdp11/ |
| opcode.s | 85 fmul r4
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/sh64/ |
| err-1.s | 16 fmul.d dr7,dr57,dr42 ! { dg-error "invalid operand" }
|
| basic-1.s | 83 fmul.d dr24,dr58,dr42
84 fmul.s fr27,fr32,fr34
|
| /external/llvm/docs/tutorial/ |
| LangImpl3.rst | 445 %multmp = fmul double %a, %a
446 %multmp1 = fmul double 2.000000e+00, %a
447 %multmp2 = fmul double %multmp1, %b
449 %multmp3 = fmul double %b, %b
505 %multmp = fmul double %a, %a
506 %multmp1 = fmul double 2.000000e+00, %a
507 %multmp2 = fmul double %multmp1, %b
509 %multmp3 = fmul double %b, %b
|
| /external/llvm/test/CodeGen/ARM/ |
| 2007-01-19-InfiniteLoop.ll | 47 %tmp631 = fmul double %tmp629a, 0.000000e+00 ; <double> [#uses=1]
58 %tmp671 = fmul double %tmp667, %tmp667 ; <double> [#uses=1]
|
| 2009-07-18-RewriterBug.ll | 95 %48 = fmul double %46, %47 ; <double> [#uses=1]
98 %51 = fmul double %49, %50 ; <double> [#uses=1]
115 %65 = fmul double %63, %64 ; <double> [#uses=1]
118 %68 = fmul double %66, %67 ; <double> [#uses=1]
274 %196 = fmul double %194, %195 ; <double> [#uses=1]
277 %199 = fmul double %197, %198 ; <double> [#uses=1]
424 %307 = fmul double %292, %303 ; <double> [#uses=1]
425 %308 = fmul double %295, %300 ; <double> [#uses=1]
427 %310 = fmul double %306, %309 ; <double> [#uses=1]
429 %312 = fmul double %300, %287 ; <double> [#uses=1
[all...] |
| /external/llvm/test/CodeGen/Mips/ |
| fmadd1.ll | 55 %mul = fmul float %a, %b
95 %mul = fmul float %a, %b
142 %mul = fmul float %a, %b
181 %mul = fmul float %a, %b
222 %mul = fmul double %a, %b
263 %mul = fmul double %a, %b
311 %mul = fmul double %a, %b
359 %mul = fmul double %a, %b
|
| /external/llvm/test/Transforms/Inline/ |
| inline-fp.ll | 111 %mul = fmul float %0, 2.620000e+03
124 %mul = fmul float %0, 2.620000e+03
|
| /external/vixl/examples/ |
| neon-matrix-multiply.cc | 36 // __ Fmul(v<v_out>.V4S(), v4.V4S(), v<s_column>.S(), 0);
52 __ Fmul(v_out, v4.V4S(), v_in, 0); // e.g. (v0.V4S(), v4.V4S(), v8.S(), 0).
|
| /external/llvm/test/Transforms/SLPVectorizer/X86/ |
| insert-element-build-vector.ll | 296 %t4 = fmul double %t0, 1.000000e+00
298 %t5 = fmul double %t1, 1.000000e+00
300 %t6 = fmul double %t2, 1.000000e+00
302 %t7 = fmul double %t3, 1.000000e+00
313 ; CHECK-DAG: %[[V6:.+]] = fmul <2 x double> <double 1.000000e+00, double 1.000000e+00>, %[[V2]]
318 ; CHECK-DAG: %[[V9:.+]] = fmul <2 x double> <double 1.000000e+00, double 1.000000e+00>, %[[V5]]
|
| operandorder.ll | 187 ; CHECK: = fmul <4 x float> %[[V1]], %[[V3]]
206 %mul6 = fmul float %3, %1
211 %mul15 = fmul float %5, %3
216 %mul25 = fmul float %7, %5
221 %mul35 = fmul float %9, %7
226 %mul45 = fmul float %10, %9
|
| /external/v8/src/arm64/ |
| codegen-arm64.cc | 529 // instead of fmul and fsub. Doing this changes the result, but since this is
598 __ Fmul(double_temp1, double_temp1, double_temp2);
601 __ Fmul(double_temp2, double_temp1, double_temp1);
603 __ Fmul(double_temp3, double_temp3, double_temp2);
609 __ Fmul(double_temp3, double_temp3, double_temp2);
630 __ Fmul(result, double_temp3, double_temp1);
|
| /external/v8/src/ppc/ |
| codegen-ppc.cc | 559 __ fmul(double_scratch1, double_scratch1, input);
565 __ fmul(double_scratch1, double_scratch1, double_scratch2);
568 __ fmul(double_scratch2, double_scratch1, double_scratch1);
569 __ fmul(result, result, double_scratch2);
571 __ fmul(result, result, double_scratch2);
596 __ fmul(result, result, double_scratch1);
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| intel.s | 664 fmul label
665 fmul st(3) label
666 fmul st,st(3) label
667 fmul st(3),st label
668 fmul DWORD PTR [ebx] label
669 fmul QWORD PTR [ebx] label
|
| /external/llvm/test/MC/X86/ |
| intel-syntax.s | 546 fmul label
566 // CHECK: fmul %st(1)
572 fmul ST(0), ST(1) label
579 // CHECK: fmul %st(0), %st(1)
585 fmul ST(1), ST(0) label
592 // CHECK: fmul %st(1)
598 fmul ST(1) label
|
| /external/llvm/lib/Transforms/Scalar/ |
| Float2Int.cpp | 126 case Instruction::FMul: return Instruction::Mul;
225 case Instruction::FMul:
277 case Instruction::FMul:
279 assert(Ops.size() == 2 && "FMul is a binary operator!");
498 case Instruction::FMul:
|
| /frameworks/rs/driver/runtime/arch/ |
| neon.ll | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXVector.td | 508 (fmul regclass:$a, regclass:$b), regclass:$c))], sop>,
524 defm VMulf : FloatBinVOp<"mul.", fmul, FMULf64rr, FMULf32rr, FMULf32rr_ftz>;
526 defm F32MAD_ftz : VMAD<"mad.ftz.f32", V4F32Regs, V2F32Regs, fadd, fmul,
528 defm F32FMA_ftz : VMAD<"fma.rn.ftz.f32", V4F32Regs, V2F32Regs, fadd, fmul,
530 defm F32MAD : VMAD<"mad.f32", V4F32Regs, V2F32Regs, fadd, fmul, FMAD32rrr,
532 defm F32FMA : VMAD<"fma.rn.f32", V4F32Regs, V2F32Regs, fadd, fmul, FMA32rrr,
576 def : Pat<(fsub V2F32Regs:$a, (fmul V2F32Regs:$b, V2F32Regs:$c)),
580 def : Pat<(fsub (fmul V2F32Regs:$a, V2F32Regs:$b), V2F32Regs:$c),
591 def : Pat<(fsub V4F32Regs:$a, (fmul V4F32Regs:$b, V4F32Regs:$c)),
595 def : Pat<(fsub (fmul V4F32Regs:$a, V4F32Regs:$b), V4F32Regs:$c)
[all...] |
| /external/llvm/test/CodeGen/Thumb/ |
| 2010-07-15-debugOrdering.ll | 33 %v_11 = fmul double %storemerge1, %storemerge1, !dbg !93 ; <double> [#uses=1]
36 %v_17 = fmul double %storemerge, %v_16, !dbg !97 ; <double> [#uses=1]
38 %v_19 = fmul double %storemerge2, %v_16, !dbg !97 ; <double> [#uses=1]
|
| /external/llvm/test/Transforms/IndVarSimplify/ |
| iv-sext.ll | 129 %tmp39 = fmul float %tmp38, %tmp1 ; <float> [#uses=2]
130 %tmp40 = fmul float %tmp39, %tmp39 ; <float> [#uses=2]
131 %tmp41 = fmul float %tmp40, %tmp40 ; <float> [#uses=1]
|
| /external/llvm/test/Transforms/InstCombine/ |
| shufflemask-undef.ll | 78 fmul <4 x float> %5, zeroinitializer ; <<4 x float>>:6 [#uses=2]
79 fmul <4 x float> %6, %6 ; <<4 x float>>:7 [#uses=1]
87 fmul <4 x float> %10, < float 5.000000e-01, float 5.000000e-01, float 5.000000e-01, float 5.000000e-01 > ; <<4 x float>>:11 [#uses=1]
|
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| avr.h | 28 #define AVR_ISA_MUL 0x0040 /* device has new core (MUL, FMUL, ...) */
106 a - `fmul' register (r16-r23)
285 AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL, 0x0308)
|
