| /prebuilts/ndk/current/platforms/android-16/arch-mips/usr/include/machine/ |
| regnum.h | 113 #define FSR (FPBASE+32)
|
| /prebuilts/ndk/current/platforms/android-17/arch-mips/usr/include/machine/ |
| regnum.h | 113 #define FSR (FPBASE+32)
|
| /prebuilts/ndk/current/platforms/android-18/arch-mips/usr/include/machine/ |
| regnum.h | 113 #define FSR (FPBASE+32)
|
| /prebuilts/ndk/current/platforms/android-19/arch-mips/usr/include/machine/ |
| regnum.h | 113 #define FSR (FPBASE+32)
|
| /prebuilts/ndk/current/platforms/android-21/arch-mips/usr/include/machine/ |
| regnum.h | 113 #define FSR (FPBASE+32)
|
| /prebuilts/ndk/current/platforms/android-21/arch-mips64/usr/include/machine/ |
| regnum.h | 113 #define FSR (FPBASE+32)
|
| /prebuilts/ndk/current/platforms/android-23/arch-mips/usr/include/machine/ |
| regnum.h | 113 #define FSR (FPBASE+32)
|
| /prebuilts/ndk/current/platforms/android-23/arch-mips64/usr/include/machine/ |
| regnum.h | 113 #define FSR (FPBASE+32)
|
| /prebuilts/ndk/current/platforms/android-24/arch-mips/usr/include/machine/ |
| regnum.h | 113 #define FSR (FPBASE+32)
|
| /prebuilts/ndk/current/platforms/android-24/arch-mips64/usr/include/machine/ |
| regnum.h | 113 #define FSR (FPBASE+32)
|
| /prebuilts/ndk/current/platforms/android-9/arch-mips/usr/include/machine/ |
| regnum.h | 113 #define FSR (FPBASE+32)
|
| /external/clang/lib/Analysis/ |
| ScanfFormatString.cpp | 535 const ScanfSpecifierResult &FSR = ParseScanfSpecifier(H, I, E, argIndex,
539 if (FSR.shouldStop())
543 if (!FSR.hasValue())
546 if (!H.HandleScanfSpecifier(FSR.getValue(), FSR.getStart(),
547 I - FSR.getStart())) {
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_from_tgsi.cpp | 51 fsr(src)
54 SrcRegister(const struct tgsi_src_register& src) : reg(src), fsr(NULL) { }
70 fsr(NULL)
79 return (dim && fsr) ? fsr->Dimension.Indirect : reg.Indirect;
84 return (dim && fsr) ? fsr->Dimension.Index : reg.Index;
96 assert(fsr && isIndirect(dim));
98 return SrcRegister(fsr->DimIndirect);
99 return SrcRegister(fsr->Indirect)
112 const struct tgsi_full_src_register *fsr; member in class:tgsi::Instruction::SrcRegister
[all...] |
| /external/google-breakpad/src/google_breakpad/common/ |
| minidump_cpu_sparc.h | 88 uint64_t fsr; /* FPU status register */ member in struct:__anon12858
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/ |
| invalid-ar.s | 123 mov.i r1 = ar.fsr
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.td | 63 def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register.
|
| SparcInstrInfo.td | 449 let Defs = [FSR] in {
452 "ld [$addr], %fsr", []>;
454 "ld [$addr], %fsr", []>;
458 "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
460 "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
490 let Defs = [FSR] in {
493 "st %fsr, [$addr]", []>;
495 "st %fsr, [$addr]", []>;
499 "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
501 "stx %fsr, [$addr]", []>, Requires<[HasV9]>
[all...] |
| /external/elfutils/backends/ |
| ia64_regs.c | 163 [28 - 8] = "fsr",
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| ia64-ic.tbl | 82 mov-from-AR-FSR; IC:mov-from-AR-M[Field(ar3) == FSR]
151 mov-to-AR-FSR; IC:mov-to-AR-M[Field(ar3) == FSR]
|
| ia64-waw.tbl | 27 AR[FSR]; IC:mov-to-AR-FSR; IC:mov-to-AR-FSR; impliedF
|
| i860-dis.c | 47 {"fir", "psr", "dirbase", "db", "fsr", "epsr", "bear", "ccr",
|
| ia64-dis.c | 209 case 28: strcpy (regname, "ar.fsr"); break;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonEarlyIfConv.cpp | 783 unsigned TR = 0, TSR = 0, FR = 0, FSR = 0, SR = 0, SSR = 0;
791 FR = RO.getReg(), FSR = RO.getSubReg();
800 FR = SR, FSR = SSR;
817 .addReg(FR, 0, FSR);
[all...] |
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 809 case Sparc::FSR:
810 Op = SparcOperand::CreateToken("%fsr", S);
938 if (name.equals("fsr")) {
939 RegNo = Sparc::FSR;
[all...] |
| /external/google-breakpad/src/processor/ |
| dump_context.cc | 501 printf(" float_save.fsr = 0x%" PRIx64 "\n",
502 context_sparc->float_save.fsr);
|
