| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.cpp | 97 // JALR, or JALR64 as appropriate for the target
108 // MIPS32r6 should use (JALR ZERO, $rs)
109 TmpInst0.setOpcode(Mips::JALR);
[all...] |
| MipsScheduleP5600.td | 57 // jalr, jr.hb, jr
|
| /toolchain/binutils/binutils-2.25/cpu/ |
| iq2000.cpu | 267 ("JR" 8) ("JALR" 9) ("JCR" 10) ("SYSCALL" 12) ("BREAK" 13) ("SLEEP" 14)
967 (dni jalr "jump and link register" (USES-RD USES-RS)
968 "jalr $rd,$rs"
[all...] |
| or1korbis.cpu | 145 ("JALR" #x12)
433 l-jalr
436 "l.jalr $rB"
[all...] |
| /external/libchrome/sandbox/linux/seccomp-bpf/ |
| syscall.cc | 404 "jalr $t9\n"
|
| /external/llvm/test/CodeGen/Mips/cconv/ |
| return-struct.ll | 169 ; N64: jalr $25
|
| /external/llvm/test/CodeGen/Mips/ |
| delay-slot-fill-forward.ll | 124 ; CHECK: jalr $25
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r2/ |
| valid-mips64r2.txt | 19 0x00 0x00 0x28 0x09 # CHECK: jalr $5, $zero
78 0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
83 0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
104 0x00 0xe0 0xf8 0x09 # CHECK: jalr $7
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| valid-mips64r3.txt | 16 0x00 0x00 0x28 0x09 # CHECK: jalr $5, $zero
75 0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
80 0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
101 0x00 0xe0 0xf8 0x09 # CHECK: jalr $7
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| valid-mips64r5.txt | 16 0x00 0x00 0x28 0x09 # CHECK: jalr $5, $zero
75 0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
80 0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
101 0x00 0xe0 0xf8 0x09 # CHECK: jalr $7
|
| /external/llvm/test/MC/Mips/ |
| relocation.s | 126 // jalr $25 // ?????: R_MIPS_JALR foo
|
| /external/pcre/dist/sljit/ |
| sljitNativeMIPS_common.c | 142 #define JALR (HI(0) | LO(9))
[all...] |
| /external/v8/test/cctest/ |
| test-macro-assembler-mips.cc | 296 __ jalr(at);
|
| /external/valgrind/coregrind/m_gdbserver/ |
| valgrind-low-mips32.c | 191 || op == 9); /* JALR */
|
| valgrind-low-mips64.c | 192 || op == 9); /* JALR */
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/epiphany/ |
| regression.d | 69 60: 1d5f 1c02 jalr r63
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| elf-rel-xgot-n64.d | 422 000000000000029c <fn\+0x29c> 0320f809 jalr t9
435 00000000000002ac <fn\+0x2ac> 0320f809 jalr t9
[all...] |
| /toolchain/binutils/binutils-2.25/gprof/po/ |
| gprof.pot | 530 msgid "[find_call] 0x%lx: jalr\n"
|
| vi.po | 612 msgid "[find_call] 0x%lx: jalr\n"
613 msgstr "[l?i_g?i_tìm] 0x%lx: jalr\n"
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| ChangeLog-2013 | 391 for the single-operand forms of JALR and JALR.HB.
392 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
[all...] |
| dlx-dis.c | 412 { OPC(JALROP), "jalr" } /* Store halfword. */
|
| /art/compiler/utils/mips64/ |
| assembler_mips64.cc | 521 void Mips64Assembler::Jalr(GpuRegister rd, GpuRegister rs) {
525 void Mips64Assembler::Jalr(GpuRegister rs) {
526 Jalr(RA, rs);
530 Jalr(ZERO, rs);
[all...] |
| /external/v8/src/mips/ |
| assembler-mips.cc | 552 ((function_field == JALR) || (rd_field == 0 && (function_field == JR))));
573 GetRdField(instr) == 0 && GetFunctionField(instr) == JALR;
580 GetRdField(instr) != 0 && GetFunctionField(instr) == JALR;
1500 void Assembler::jalr(Register rs, Register rd) { function in class:v8::internal::Assembler
[all...] |
| /toolchain/binutils/binutils-2.25/gold/ |
| mips.cc | [all...] |
| /toolchain/binutils/binutils-2.25/ld/testsuite/ |
| ChangeLog-9303 | 205 * ld-mips-elf/relax-jalr-n32.d: Fix little endian test failure.
206 * ld-mips-elf/relax-jalr-n32-shared.d: Likewise.
207 * ld-mips-elf/relax-jalr-n64.d: Likewise.
208 * ld-mips-elf/relax-jalr-n64-shared.d: Likewise.
376 * ld-mips-elf/relax-jalr.s: Fix testsuite breakage.
377 * ld-mips-elf/relax-jalr-n32.d: Likewise.
378 * ld-mips-elf/relax-jalr-n32-shared.d: Likewise.
379 * ld-mips-elf/relax-jalr-n64.d: Likewise.
380 * ld-mips-elf/relax-jalr-n64-shared.d: Likewise.
792 * ld-mips-elf/relax-jalr.s, ld-mips-elf/relax-jalr-n32.d
[all...] |
