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      1 //==- MipsScheduleP5600.td - P5600 Scheduling Definitions --*- tablegen -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 def MipsP5600Model : SchedMachineModel {
     11   int IssueWidth = 2; // 2x dispatched per cycle
     12   int MicroOpBufferSize = 48; // min(48, 48, 64)
     13   int LoadLatency = 4;
     14   int MispredictPenalty = 8; // TODO: Estimated
     15 
     16   let CompleteModel = 1;
     17 }
     18 
     19 let SchedModel = MipsP5600Model in {
     20 
     21 // ALQ Pipelines
     22 // =============
     23 
     24 def P5600ALQ : ProcResource<1> { let BufferSize = 16; }
     25 def P5600IssueALU : ProcResource<1> { let Super = P5600ALQ; }
     26 
     27 // ALU Pipeline
     28 // ------------
     29 
     30 def P5600WriteALU : SchedWriteRes<[P5600IssueALU]>;
     31 
     32 // and, lui, nor, or, slti, sltiu, sub, subu, xor
     33 def : ItinRW<[P5600WriteALU],
     34              [II_AND, II_LUI, II_NOR, II_OR, II_SLTI_SLTIU, II_SUBU, II_XOR]>;
     35 
     36 // AGQ Pipelines
     37 // =============
     38 
     39 def P5600AGQ : ProcResource<3> { let BufferSize = 16; }
     40 def P5600IssueAL2 : ProcResource<1> { let Super = P5600AGQ; }
     41 def P5600IssueCTISTD : ProcResource<1> { let Super = P5600AGQ; }
     42 def P5600IssueLDST : ProcResource<1> { let Super = P5600AGQ; }
     43 
     44 def P5600AL2Div : ProcResource<1>;
     45 // Pseudo-resource used to block CTISTD when handling multi-pipeline splits.
     46 def P5600CTISTD : ProcResource<1>;
     47 
     48 // CTISTD Pipeline
     49 // ---------------
     50 
     51 def P5600WriteJump : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]>;
     52 def P5600WriteJumpAndLink : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]> {
     53   let Latency = 2;
     54 }
     55 
     56 // b, beq, beql, bg[et]z, bl[et]z, bne, bnel, j, syscall, jal, bltzal, jalx,
     57 // jalr, jr.hb, jr
     58 def : ItinRW<[P5600WriteJump], [II_B, II_BCC, II_BCCZ, II_BCCZAL, II_J, II_JR]>;
     59 def : ItinRW<[P5600WriteJumpAndLink], [II_JAL, II_JALR]>;
     60 
     61 // LDST Pipeline
     62 // -------------
     63 
     64 def P5600WriteLoad : SchedWriteRes<[P5600IssueLDST]> {
     65   let Latency = 4;
     66 }
     67 
     68 def P5600WriteLoadShifted : SchedWriteRes<[P5600IssueLDST, P5600CTISTD]> {
     69   let Latency = 4;
     70 }
     71 
     72 def P5600WritePref : SchedWriteRes<[P5600IssueLDST]>;
     73 
     74 def P5600WriteStore : SchedWriteRes<[P5600IssueLDST, P5600CTISTD]> {
     75   // FIXME: This is a bit pessimistic. P5600CTISTD is only used during cycle 2
     76   //        not during 0, 1, and 2.
     77   let ResourceCycles = [ 1, 3 ];
     78 }
     79 
     80 def P5600WriteGPRFromBypass : SchedWriteRes<[P5600IssueLDST]> {
     81   let Latency = 2;
     82 }
     83 
     84 def P5600WriteStoreFromOtherUnits : SchedWriteRes<[P5600IssueLDST]>;
     85 def P5600WriteLoadToOtherUnits : SchedWriteRes<[P5600IssueLDST]> {
     86   let Latency = 0;
     87 }
     88 
     89 // l[bhw], l[bh]u, ll
     90 def : ItinRW<[P5600WriteLoad], [II_LB, II_LBU, II_LH, II_LHU, II_LW, II_LWU]>;
     91 
     92 // lw[lr]
     93 def : ItinRW<[P5600WriteLoadShifted], [II_LWL, II_LWR]>;
     94 
     95 // s[bhw], sw[lr]
     96 def : ItinRW<[P5600WriteStore], [II_SB, II_SH, II_SW, II_SWL, II_SWR]>;
     97 
     98 // pref
     99 // (this instruction does not exist in the backend yet)
    100 def : ItinRW<[P5600WritePref], []>;
    101 
    102 // sc
    103 // (this instruction does not exist in the backend yet)
    104 def : ItinRW<[P5600WriteStore], []>;
    105 
    106 // LDST is also used in moves from general purpose registers to floating point
    107 // and MSA.
    108 def P5600WriteMoveGPRToOtherUnits : SchedWriteRes<[P5600IssueLDST]> {
    109   let Latency = 0;
    110 }
    111 
    112 // AL2 Pipeline
    113 // ------------
    114 
    115 def P5600WriteAL2 : SchedWriteRes<[P5600IssueAL2]>;
    116 def P5600WriteAL2BitExt : SchedWriteRes<[P5600IssueAL2]> { let Latency = 2; }
    117 def P5600WriteAL2ShadowMov : SchedWriteRes<[P5600IssueAL2]> { let Latency = 2; }
    118 def P5600WriteAL2CondMov : SchedWriteRes<[P5600IssueAL2, P5600CTISTD]> {
    119   let Latency = 2;
    120 }
    121 def P5600WriteAL2Div : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> {
    122   // Estimated worst case
    123   let Latency = 34;
    124   let ResourceCycles = [1, 34];
    125 }
    126 def P5600WriteAL2DivU : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> {
    127   // Estimated worst case
    128   let Latency = 34;
    129   let ResourceCycles = [1, 34];
    130 }
    131 def P5600WriteAL2Mul : SchedWriteRes<[P5600IssueAL2]> { let Latency = 3; }
    132 def P5600WriteAL2Mult: SchedWriteRes<[P5600IssueAL2]> { let Latency = 5; }
    133 def P5600WriteAL2MAdd: SchedWriteRes<[P5600IssueAL2, P5600CTISTD]> {
    134   let Latency = 5;
    135 }
    136 
    137 // clo, clz, di, mfhi, mflo
    138 def : ItinRW<[P5600WriteAL2], [II_CLO, II_CLZ, II_MFHI_MFLO]>;
    139 
    140 // ehb, rdhwr, rdpgpr, wrpgpr, wsbh
    141 def : ItinRW<[P5600WriteAL2ShadowMov], [II_RDHWR]>;
    142 
    143 // mov[nz]
    144 def : ItinRW<[P5600WriteAL2CondMov], [II_MOVN, II_MOVZ]>;
    145 
    146 // divu?
    147 def : ItinRW<[P5600WriteAL2Div], [II_DIV]>;
    148 def : ItinRW<[P5600WriteAL2DivU], [II_DIVU]>;
    149 
    150 // mul
    151 def : ItinRW<[P5600WriteAL2Mul], [II_MUL]>;
    152 // multu?, multu?
    153 def : ItinRW<[P5600WriteAL2Mult], [II_MULT, II_MULTU]>;
    154 // maddu?, msubu?, mthi, mtlo
    155 def : ItinRW<[P5600WriteAL2MAdd],
    156              [II_MADD, II_MADDU, II_MSUB, II_MSUBU, II_MTHI_MTLO]>;
    157 
    158 // ext, ins
    159 def : ItinRW<[P5600WriteAL2BitExt],
    160              [II_EXT, II_INS]>;
    161 
    162 // Either ALU or AL2 Pipelines
    163 // ---------------------------
    164 //
    165 // Some instructions can choose between ALU and AL2, but once dispatched to
    166 // ALQ or AGQ respectively they are committed to that path.
    167 // The decision is based on the outcome of the most recent selection when the
    168 // choice was last available. For now, we assume ALU is always chosen.
    169 
    170 def P5600WriteEitherALU : SchedWriteVariant<
    171   // FIXME: Implement selection predicate
    172   [SchedVar<SchedPredicate<[{1}]>, [P5600WriteALU]>,
    173    SchedVar<SchedPredicate<[{0}]>, [P5600WriteAL2]>
    174   ]>;
    175 
    176 // add, addi, addiu, addu, andi, ori, rotr, se[bh], sllv?, sr[al]v?, slt, sltu,
    177 // xori
    178 def : ItinRW<[P5600WriteEitherALU],
    179              [II_ADDI, II_ADDIU, II_ANDI, II_ORI, II_ROTR, II_SEB, II_SEH,
    180               II_SLT_SLTU, II_SLL, II_SRA, II_SRL, II_XORI, II_ADDU, II_SLLV,
    181               II_SRAV, II_SRLV]>;
    182 
    183 // FPU Pipelines
    184 // =============
    185 
    186 def P5600FPQ : ProcResource<3> { let BufferSize = 16; }
    187 def P5600IssueFPUS : ProcResource<1> { let Super = P5600FPQ; }
    188 def P5600IssueFPUL : ProcResource<1> { let Super = P5600FPQ; }
    189 def P5600IssueFPULoad : ProcResource<1> { let Super = P5600FPQ; }
    190 
    191 def P5600FPUDivSqrt : ProcResource<2>;
    192 
    193 def P5600WriteFPUS : SchedWriteRes<[P5600IssueFPUS]>;
    194 def P5600WriteFPUL : SchedWriteRes<[P5600IssueFPUL]> { let Latency = 4; }
    195 def P5600WriteFPUL_MADDSUB : SchedWriteRes<[P5600IssueFPUL]> { let Latency = 6; }
    196 def P5600WriteFPUDivS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
    197   // Best/Common/Worst case = 7 / 23 / 27
    198   let Latency = 23; // Using common case
    199   let ResourceCycles = [ 1, 23 ];
    200 }
    201 def P5600WriteFPUDivD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
    202   // Best/Common/Worst case = 7 / 31 / 35
    203   let Latency = 31; // Using common case
    204   let ResourceCycles = [ 1, 31 ];
    205 }
    206 def P5600WriteFPURcpS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
    207   // Best/Common/Worst case = 7 / 19 / 23
    208   let Latency = 19; // Using common case
    209   let ResourceCycles = [ 1, 19 ];
    210 }
    211 def P5600WriteFPURcpD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
    212   // Best/Common/Worst case = 7 / 27 / 31
    213   let Latency = 27; // Using common case
    214   let ResourceCycles = [ 1, 27 ];
    215 }
    216 def P5600WriteFPURsqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
    217   // Best/Common/Worst case = 7 / 27 / 27
    218   let Latency = 27; // Using common case
    219   let ResourceCycles = [ 1, 27 ];
    220 }
    221 def P5600WriteFPURsqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
    222   // Best/Common/Worst case = 7 / 27 / 31
    223   let Latency = 27; // Using common case
    224   let ResourceCycles = [ 1, 27 ];
    225 }
    226 def P5600WriteFPUSqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
    227   // Best/Common/Worst case = 7 / 27 / 31
    228   let Latency = 27; // Using common case
    229   let ResourceCycles = [ 1, 27 ];
    230 }
    231 def P5600WriteFPUSqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
    232   // Best/Common/Worst case = 7 / 35 / 39
    233   let Latency = 35; // Using common case
    234   let ResourceCycles = [ 1, 35 ];
    235 }
    236 def P5600WriteMSAShortLogic : SchedWriteRes<[P5600IssueFPUS]>;
    237 def P5600WriteMSAShortInt : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 2; }
    238 def P5600WriteMoveOtherUnitsToFPU : SchedWriteRes<[P5600IssueFPUS]>;
    239 
    240 // FPUS is also used in moves from floating point and MSA registers to general
    241 // purpose registers.
    242 def P5600WriteMoveFPUSToOtherUnits : SchedWriteRes<[P5600IssueFPUS]> {
    243   let Latency = 0;
    244 }
    245 
    246 // FPUL is also used in moves from floating point and MSA registers to general
    247 // purpose registers.
    248 def P5600WriteMoveFPULToOtherUnits : SchedWriteRes<[P5600IssueFPUL]>;
    249 
    250 // Short Pipe
    251 // ----------
    252 //
    253 // abs.[ds], abs.ps, bc1[tf]l?, mov[tf].[ds], mov[tf], mov.[ds], [cm][ft]c1,
    254 // m[ft]hc1, neg.[ds], neg.ps, nor.v, nori.b, or.v, ori.b, xor.v, xori.b,
    255 // sdxc1, sdc1, st.[bhwd], swc1, swxc1
    256 def : ItinRW<[P5600WriteFPUS], [II_ABS, II_MOVF_D, II_MOVF_S, II_MOVT_D,
    257                                 II_MOVT_S, II_MOV_D, II_MOV_S, II_NEG]>;
    258 
    259 // adds_a.[bhwd], adds_[asu].[bhwd], addvi?.[bhwd], asub_[us].[bhwd],
    260 // aver?_[us].[bhwd]
    261 def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADD_A_[BHWD]$")>;
    262 def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADDS_[ASU]_[BHWD]$")>;
    263 // TODO: ADDVI_[BHW] might be 1 cycle latency rather than 2. Need to confirm it.
    264 def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADDVI?_[BHWD]$")>;
    265 def : InstRW<[P5600WriteMSAShortInt], (instregex "^ASUB_[US].[BHWD]$")>;
    266 def : InstRW<[P5600WriteMSAShortInt], (instregex "^AVER?_[US].[BHWD]$")>;
    267 
    268 // and.v, andi.b, move.v, ldi.[bhwd]
    269 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^MOVE_V$")>;
    270 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^LDI_[BHWD]$")>;
    271 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)_V$")>;
    272 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)I_B$")>;
    273 
    274 // Long Pipe
    275 // ----------
    276 //
    277 // add.[ds], add.ps, cvt.d.[sw], cvt.s.[dw], cvt.w.[sd], cvt.[sw].ps,
    278 // cvt.ps.[sw], c.<cc>.[ds], c.<cc>.ps, mul.[ds], mul.ps, sub.[ds], sub.ps,
    279 // trunc.w.[ds], trunc.w.ps
    280 def : ItinRW<[P5600WriteFPUL],
    281              [II_ADD_D, II_ADD_S, II_CVT, II_C_CC_D, II_C_CC_S, II_MUL_D,
    282               II_MUL_S, II_SUB_D, II_SUB_S, II_TRUNC]>;
    283 
    284 // div.[ds], div.ps
    285 def : ItinRW<[P5600WriteFPUDivS], [II_DIV_S]>;
    286 def : ItinRW<[P5600WriteFPUDivD], [II_DIV_D]>;
    287 
    288 // sqrt.[ds], sqrt.ps
    289 def : ItinRW<[P5600WriteFPUSqrtS], [II_SQRT_S]>;
    290 def : ItinRW<[P5600WriteFPUSqrtD], [II_SQRT_D]>;
    291 
    292 // madd.[ds], msub.[ds], nmadd.[ds], nmsub.[ds],
    293 // Operand 0 is read on cycle 5. All other operands are read on operand 0.
    294 def : ItinRW<[SchedReadAdvance<5>, P5600WriteFPUL_MADDSUB],
    295              [II_MADD_D, II_MADD_S, II_MSUB_D, II_MSUB_S, II_NMADD_D,
    296               II_NMADD_S, II_NMSUB_D, II_NMSUB_S]>;
    297 
    298 // madd.ps, msub.ps, nmadd.ps, nmsub.ps
    299 // Operand 0 and 1 are read on cycle 5. All others are read on operand 0.
    300 // (none of these instructions exist in the backend yet)
    301 
    302 // Load Pipe
    303 // ---------
    304 //
    305 // This is typically used in conjunction with the load pipeline under the AGQ
    306 // All the instructions are in the 'Tricky Instructions' section.
    307 
    308 def P5600WriteLoadOtherUnitsToFPU : SchedWriteRes<[P5600IssueFPULoad]> {
    309   let Latency = 4;
    310 }
    311 
    312 // Tricky Instructions
    313 // ===================
    314 //
    315 // These instructions are split across multiple uops (in different pipelines)
    316 // that must cooperate to complete the operation
    317 
    318 // FIXME: This isn't quite right since the implementation of WriteSequence
    319 //        current aggregates the resources and ignores the exact cycle they are
    320 //        used.
    321 def P5600WriteMoveGPRToFPU : WriteSequence<[P5600WriteMoveGPRToOtherUnits,
    322                                             P5600WriteMoveOtherUnitsToFPU]>;
    323 
    324 // FIXME: This isn't quite right since the implementation of WriteSequence
    325 //        current aggregates the resources and ignores the exact cycle they are
    326 //        used.
    327 def P5600WriteMoveFPUToGPR : WriteSequence<[P5600WriteMoveFPUSToOtherUnits,
    328                                             P5600WriteGPRFromBypass]>;
    329 
    330 // FIXME: This isn't quite right since the implementation of WriteSequence
    331 //        current aggregates the resources and ignores the exact cycle they are
    332 //        used.
    333 def P5600WriteStoreFPUS : WriteSequence<[P5600WriteMoveFPUSToOtherUnits,
    334                                          P5600WriteStoreFromOtherUnits]>;
    335 
    336 // FIXME: This isn't quite right since the implementation of WriteSequence
    337 //        current aggregates the resources and ignores the exact cycle they are
    338 //        used.
    339 def P5600WriteStoreFPUL : WriteSequence<[P5600WriteMoveFPULToOtherUnits,
    340                                          P5600WriteStoreFromOtherUnits]>;
    341 
    342 // FIXME: This isn't quite right since the implementation of WriteSequence
    343 //        current aggregates the resources and ignores the exact cycle they are
    344 //        used.
    345 def P5600WriteLoadFPU : WriteSequence<[P5600WriteLoadToOtherUnits,
    346                                        P5600WriteLoadOtherUnitsToFPU]>;
    347 
    348 // ctc1, mtc1, mthc1
    349 def : ItinRW<[P5600WriteMoveGPRToFPU], [II_CTC1, II_MTC1, II_MTHC1]>;
    350 
    351 // bc1[ft], cfc1, mfc1, mfhc1, movf, movt
    352 def : ItinRW<[P5600WriteMoveFPUToGPR],
    353              [II_BC1F, II_BC1T, II_CFC1, II_MFC1, II_MFHC1, II_MOVF, II_MOVT]>;
    354 
    355 // swc1, swxc1, st.[bhwd]
    356 def : ItinRW<[P5600WriteStoreFPUS], [II_SWC1, II_SWXC1]>;
    357 def : InstRW<[P5600WriteStoreFPUS], (instregex "^ST_[BHWD]$")>;
    358 
    359 // movn.[ds], movz.[ds]
    360 def : ItinRW<[P5600WriteStoreFPUL], [II_MOVN_D, II_MOVN_S, II_MOVZ_D, II_MOVZ_S]>;
    361 
    362 // l[dw]x?c1, ld.[bhwd]
    363 def : ItinRW<[P5600WriteLoadFPU], [II_LDC1, II_LDXC1, II_LWC1, II_LWXC1]>;
    364 def : InstRW<[P5600WriteLoadFPU], (instregex "LD_[BHWD]")>;
    365 
    366 // Unsupported Instructions
    367 // ========================
    368 //
    369 // The following instruction classes are never valid on P5600.
    370 //   II_DADDIU, II_DADDU, II_DMFC1, II_DMTC1, II_DMULT, II_DMULTU, II_DROTR,
    371 //   II_DROTR32, II_DROTRV, II_DDIV, II_DSLL, II_DSLL32, II_DSLLV, II_DSRA,
    372 //   II_DSRA32, II_DSRAV, II_DSRL, II_DSRL32, II_DSRLV, II_DSUBU, II_DDIVU,
    373 //   II_JALRC, II_LD, II_LD[LR], II_LUXC1, II_RESTORE, II_SAVE, II_SD, II_SDC1,
    374 //   II_SDL, II_SDR, II_SDXC1
    375 //
    376 // The following instructions are never valid on P5600.
    377 //   addq.ph, rdhwr, repl.ph, repl.qb, subq.ph, subu_s.qb
    378 //
    379 // Guesswork
    380 // =========
    381 //
    382 // This section is largely temporary guesswork.
    383 
    384 // ceil.[lw].[ds], floor.[lw].[ds]
    385 // Reason behind guess: trunc.[lw].ds and the various cvt's are in FPUL
    386 def : ItinRW<[P5600WriteFPUL], [II_CEIL, II_FLOOR, II_ROUND]>;
    387 
    388 // rotrv
    389 // Reason behind guess: rotr is in the same category and the two register forms
    390 //                      generally follow the immediate forms in this category
    391 def : ItinRW<[P5600WriteEitherALU], [II_ROTRV]>;
    392 }
    393