| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64r2.s | 31 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /art/runtime/interpreter/mterp/mips64/ |
| header.S | 232 mthc1 AT, \reg
|
| /external/llvm/test/CodeGen/Mips/ |
| fmadd1.ll | 200 ; 32R2: mthc1 $zero, $[[T2]]
241 ; 32R2: mthc1 $zero, $[[T2]]
285 ; 32R2-NAN: mthc1 $zero, $[[T2]]
333 ; 32R2-NAN: mthc1 $zero, $[[T2]]
|
| select.ll | 174 ; 32R2-DAG: mthc1 $7, $[[F0]]
179 ; 32R6-DAG: mthc1 $7, $[[F0]]
471 ; 32R2-DAG: mthc1 $7, $[[F2]]
478 ; 32R6-DAG: mthc1 $7, $[[F2]]
|
| /external/llvm/test/MC/Mips/ |
| micromips-fpu-instructions.s | 57 # CHECK-EL: mthc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x38]
122 # CHECK-EB: mthc1 $6, $f8 # encoding: [0x54,0xc8,0x38,0x3b]
183 mthc1 $6, $f8
|
| mips-fpu-instructions.s | 173 # CHECK: mthc1 $17, $f6 # encoding: [0x00,0x30,0xf1,0x44]
208 mthc1 $17, $f6
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 634 // When mthc1 is available, use:
636 // mthc1 Hi, $fp
667 // MTHC1 is one of two instructions that are affected since they are
|
| MipsSEFrameLowering.cpp | 264 /// expandBuildPairF64 does, for the case when ABI is fpxx and mthc1 is not
271 // For fpxx and when mthc1 is not available, use:
290 // the cases where mthc1 is not available). 64-bit architectures and
[all...] |
| MipsScheduleP5600.td | 348 // ctc1, mtc1, mthc1
|
| MipsInstrFPU.td | 376 def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
378 def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
|
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| callabi.ll | 384 ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f12
403 ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f12
410 ; 32R2-DAG: mthc1 $[[REG_FPCONST_2]], $f14
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32r2.s | 53 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| basic_operations_float.ll | 213 ; ALL-NOT: mthc1
233 ; ALL-NOT: mthc1
|
| /art/compiler/utils/mips64/ |
| assembler_mips64_test.cc | 558 TEST_F(AssemblerMIPS64Test, Mthc1) {
559 DriverStr(RepeatRF(&mips64::Mips64Assembler::Mthc1, "mthc1 ${reg1}, ${reg2}"), "Mthc1");
[all...] |
| assembler_mips64.h | 309 void Mthc1(GpuRegister rt, FpuRegister fs);
|
| /external/v8/src/mips/ |
| macro-assembler-mips.cc | [all...] |
| macro-assembler-mips.h | 258 Mthc1(src_high, dst);
269 Mthc1(src_high, dst);
788 void Mthc1(Register rt, FPURegister fs);
[all...] |
| disasm-mips.cc | [all...] |
| /art/compiler/utils/mips/ |
| assembler_mips_test.cc | 694 TEST_F(AssemblerMIPSTest, Mthc1) {
695 DriverStr(RepeatRF(&mips::MipsAssembler::Mthc1, "mthc1 ${reg1}, ${reg2}"), "Mthc1");
[all...] |
| /art/runtime/interpreter/mterp/mips/ |
| header.S | 422 mthc1 AT, rlo; \
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| set-arch.s | 286 mthc1 $17, $f0
|
| mxu.d | 15 [0-9a-f]+ <[^>]*> 44e21002 mthc1 v0,\$f2
16 [0-9a-f]+ <[^>]*> 44e21002 mthc1 v0,\$f2
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| select.ll | 247 ; CMOV-32R2-R5: mthc1 $6, $[[F0]]
253 ; SEL-32: mthc1 $6, $[[F0]]
|
| /art/disassembler/ |
| disassembler_mips.cc | 350 { kFpMask | (0x1f << 21), kCop1 | (0x07 << 21), "mthc1", "Td" },
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| valid-mips32r2-el.txt | 119 0x00 0x80 0xe0 0x44 # CHECK: mthc1 $zero, $f16
|
