| /external/llvm/test/CodeGen/X86/ |
| copy-propagation.ll | 10 ; reg1 = copy reg2
12 ; reg2 = copy reg1
17 ; reg1 = copy reg2
20 ; reg2 = copy reg1
|
| 2011-12-15-vec_shift.ll | 9 ; CHECK-W-SSE4: psllw $4, [[REG1:%xmm.]]
10 ; CHECK-W-SSE4: pblendvb [[REG1]],{{ %xmm.}}
14 ; CHECK-WO-SSE4: psllw $5, [[REG1:%xmm.]]
|
| lea-opt.ll | 37 ; CHECK: leaq (%rdi,%rdi,2), [[REG1:%[a-z]+]]
38 ; CHECK: movl arr1(,[[REG1]],4), {{.*}}
39 ; CHECK: leaq arr1+4(,[[REG1]],4), [[REG2:%[a-z]+]]
40 ; CHECK: subl arr1+4(,[[REG1]],4), {{.*}}
41 ; CHECK: leaq arr1+8(,[[REG1]],4), [[REG3:%[a-z]+]]
42 ; CHECK: addl arr1+8(,[[REG1]],4), {{.*}}
77 ; CHECK: leaq (%rdi,%rdi,2), [[REG1:%[a-z]+]]
78 ; CHECK: leaq arr1+4(,[[REG1]],4), [[REG2:%[a-z]+]]
81 ; CHECK: leaq arr1+8(,[[REG1]],4), [[REG3:%[a-z]+]]
118 ; CHECK: imulq {{.*}}, [[REG1:%[a-z]+]
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| lxvw4x-bug.ll | 18 ; CHECK: lxvd2x [[REG1:[0-9]+]], {{[0-9]+}}, [[REG0]]
19 ; CHECK: xxswapd [[REG1]], [[REG1]]
|
| mcm-10.ll | 20 ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
21 ; CHECK: lwa {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
23 ; CHECK: stw {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
|
| select-i1-vs-i1.ll | 20 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
21 ; CHECK: isel 3, 7, 8, [[REG1]]
36 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
37 ; CHECK: isel 3, 7, 8, [[REG1]]
52 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
53 ; CHECK: isel 3, 7, 8, [[REG1]]
68 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
69 ; CHECK: isel 3, 7, 8, [[REG1]]
84 ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
85 ; CHECK: isel 3, 7, 8, [[REG1]]
[all...] |
| crbits.ll | 15 ; CHECK-DAG: li [[REG1:[0-9]+]], 1
21 ; CHECK: isel 3, 0, [[REG1]], [[REG4]]
35 ; CHECK-DAG: li [[REG1:[0-9]+]], 1
41 ; CHECK: isel 3, 0, [[REG1]], [[REG4]]
57 ; CHECK-DAG: li [[REG1:[0-9]+]], 1
64 ; CHECK: isel 3, 0, [[REG1]], [[REG4]]
76 ; CHECK: and [[REG1:[0-9]+]], 3, 4
77 ; CHECK: or 3, [[REG1]], 5
90 ; CHECK-DAG: and [[REG1:[0-9]+]], 3, 4
93 ; CHECK-DAG: andi. {{[0-9]+}}, [[REG1]],
[all...] |
| crbit-asm.ll | 15 ; CHECK-DAG: li [[REG1:[0-9]+]], 0
20 ; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
34 ; CHECK-DAG: li [[REG1:[0-9]+]], 0
39 ; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
50 ; CHECK-DAG: li [[REG1:[0-9]+]], 0
55 ; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]]
|
| mcm-11.ll | 20 ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
21 ; CHECK: lwa {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
23 ; CHECK: stw {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
|
| cc.ll | 21 ; CHECK: mfcr [[REG1:[0-9]+]]
24 ; CHECK-DAG: stw [[REG1]], 8(1)
54 ; CHECK: mfcr [[REG1:[0-9]+]]
57 ; CHECK-DAG: stw [[REG1]], 8(1)
|
| mcm-2.ll | 21 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
22 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
29 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
30 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
|
| mcm-3.ll | 21 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
22 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
32 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
33 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
|
| /external/llvm/test/CodeGen/SystemZ/ |
| vec-move-15.ll | 24 ; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
25 ; CHECK: vuphb %v24, [[REG1]]
43 ; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)
44 ; CHECK: vuphb [[REG2:%v[0-9]+]], [[REG1]]
55 ; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
56 ; CHECK: vuphh %v24, [[REG1]]
74 ; CHECK: vlreph [[REG1:%v[0-9]+]], 0(%r2)
75 ; CHECK: vuphb [[REG2:%v[0-9]+]], [[REG1]]
87 ; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)
88 ; CHECK: vuphh [[REG2:%v[0-9]+]], [[REG1]]
[all...] |
| vec-move-16.ll | 24 ; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
25 ; CHECK: vuplhb %v24, [[REG1]]
43 ; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)
44 ; CHECK: vuplhb [[REG2:%v[0-9]+]], [[REG1]]
55 ; CHECK: vlrepg [[REG1:%v[0-9]+]], 0(%r2)
56 ; CHECK: vuplhh %v24, [[REG1]]
74 ; CHECK: vlreph [[REG1:%v[0-9]+]], 0(%r2)
75 ; CHECK: vuplhb [[REG2:%v[0-9]+]], [[REG1]]
87 ; CHECK: vlrepf [[REG1:%v[0-9]+]], 0(%r2)
88 ; CHECK: vuplhh [[REG2:%v[0-9]+]], [[REG1]]
[all...] |
| asm-18.ll | 10 ; CHECK-DAG: lfh [[REG1:%r[0-5]]], 0(%r2)
14 ; CHECK: blah [[REG1]], [[REG2]], [[REG3]], [[REG4]]
15 ; CHECK-DAG: stfh [[REG1]], 0(%r2)
42 ; CHECK-DAG: risbhg [[REG1:%r[0-5]]], %r2, 0, 159, 32
44 ; CHECK: stepa [[REG1]], %r2, %r3
45 ; CHECK: risbhg {{%r[0-5]}}, [[REG1]], 0, 159, 0
58 ; CHECK-DAG: lbh [[REG1:%r[0-5]]], 0(%r2)
62 ; CHECK: blah [[REG1]], [[REG2]]
82 ; CHECK-DAG: lhh [[REG1:%r[0-5]]], 0(%r2)
86 ; CHECK: blah [[REG1]], [[REG2]
[all...] |
| /external/libvpx/libvpx/vpx_dsp/mips/ |
| idct16x16_msa.c | 16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7,
24 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
40 DOTP_CONST_PAIR(reg1, reg15, cospi_30_64, cospi_2_64, reg1, reg15);
43 reg9 = reg1 - loc2;
44 reg1 = reg1 + loc2;
57 loc1 = reg1 + reg13
110 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-bitfield-extract.ll | 76 ; CHECK: ldr [[REG1:x[0-9]+]],
77 ; CHECK-NEXT: bfxil [[REG1]], x1, #16, #24
78 ; CHECK-NEXT: str [[REG1]],
92 ; CHECK: ldr [[REG1:w[0-9]+]],
93 ; CHECK-NEXT: bfxil [[REG1]], w1, #16, #3
94 ; CHECK-NEXT: str [[REG1]],
109 ; CHECK: ldr [[REG1:w[0-9]+]],
110 ; CHECK-NEXT: bfxil [[REG1]], w1, #16, #3
112 ; CHECK-NEXT: lsr [[REG2:w[0-9]+]], [[REG1]], #2
130 ; CHECK: ldr [[REG1:w[0-9]+]]
[all...] |
| arm64-fast-isel-addr-offset.ll | 11 ; CHECK: ldr x[[REG1:[0-9]+]], [x[[REG]], _sortlist@GOTPAGEOFF]
13 ; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]]
24 ; CHECK: ldr x[[REG1:[0-9]+]], [x[[REG]], _sortlist2@GOTPAGEOFF]
26 ; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]]
|
| /art/compiler/utils/mips/ |
| assembler_mips_test.cc | 259 DriverStr(RepeatRRR(&mips::MipsAssembler::Addu, "addu ${reg1}, ${reg2}, ${reg3}"), "Addu");
263 DriverStr(RepeatRRIb(&mips::MipsAssembler::Addiu, -16, "addiu ${reg1}, ${reg2}, {imm}"), "Addiu");
267 DriverStr(RepeatRRR(&mips::MipsAssembler::Subu, "subu ${reg1}, ${reg2}, ${reg3}"), "Subu");
271 DriverStr(RepeatRR(&mips::MipsAssembler::MultR2, "mult ${reg1}, ${reg2}"), "MultR2");
275 DriverStr(RepeatRR(&mips::MipsAssembler::MultuR2, "multu ${reg1}, ${reg2}"), "MultuR2");
279 DriverStr(RepeatRR(&mips::MipsAssembler::DivR2, "div $zero, ${reg1}, ${reg2}"), "DivR2Basic");
283 DriverStr(RepeatRR(&mips::MipsAssembler::DivuR2, "divu $zero, ${reg1}, ${reg2}"), "DivuR2Basic");
287 DriverStr(RepeatRRR(&mips::MipsAssembler::MulR2, "mul ${reg1}, ${reg2}, ${reg3}"), "MulR2");
291 DriverStr(RepeatRRR(&mips::MipsAssembler::DivR2, "div $zero, ${reg2}, ${reg3}\nmflo ${reg1}"),
296 DriverStr(RepeatRRR(&mips::MipsAssembler::ModR2, "div $zero, ${reg2}, ${reg3}\nmfhi ${reg1}"),
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| eh-dispcont.ll | 46 ; ARM-PIC: adr [[REG1:r[0-9]+]], [[LJTI:.*]]
47 ; ARM-PIC: ldr [[REG0:r[0-9]+]], [r{{[0-9]+}}, [[REG1]]]
48 ; ARM-PIC: add pc, [[REG0]], [[REG1]]
57 ; ARM-NOPIC: adr [[REG1:r[0-9]+]], [[LJTI:.*]]
58 ; ARM-NOPIC: ldr [[REG0:r[0-9]+]], [r{{[0-9]+}}, [[REG1]]]
68 ; THUMB1-PIC: adr [[REG1:r[0-9]+]], [[LJTI:.*]]
69 ; THUMB1-PIC: adds [[REG0:r[0-9]+]], [[REG0]], [[REG1]]
71 ; THUMB1-PIC: adds [[REG0]], [[REG0]], [[REG1]]
81 ; THUMB1-NOPIC: adr [[REG1:r[0-9]+]], [[LJTI:.*]]
82 ; THUMB1-NOPIC: adds [[REG0:r[0-9]+]], [[REG0]], [[REG1]]
[all...] |
| /art/compiler/utils/arm/ |
| assembler_arm32_test.cc | 670 "sbfx{cond} {reg1}, {reg2}, #{imm1}, #{imm2}"), "sbfx");
694 "ubfx{cond} {reg1}, {reg2}, #{imm1}, #{imm2}"), "ubfx");
698 T4Helper(&arm::Arm32Assembler::mul, true, "mul{cond} {reg1}, {reg2}, {reg3}", "mul");
702 T5Helper(&arm::Arm32Assembler::mla, true, "mla{cond} {reg1}, {reg2}, {reg3}, {reg4}", "mla");
706 T5Helper(&arm::Arm32Assembler::umull, true, "umull{cond} {reg1}, {reg2}, {reg3}, {reg4}",
707 "umull", "{reg1}={reg2}"); // Skip the cases where reg1 == reg2.
711 T5Helper(&arm::Arm32Assembler::smull, true, "smull{cond} {reg1}, {reg2}, {reg3}, {reg4}",
712 "smull", "{reg1}={reg2}"); // Skip the cases where reg1 == reg2
[all...] |
| assembler_arm_test.h | 77 template <typename Reg1, typename Reg2>
78 std::string RepeatTemplatedRRIIC(void (Ass::*f)(Reg1, Reg2, Imm, Imm, Cond),
79 const std::vector<Reg1*> reg1_registers,
81 std::string (AssemblerArmTest::*GetName1)(const Reg1&),
128 for (auto reg1 : reg1_registers) {
131 std::string reg1_string = (this->*GetName1)(*reg1);
153 (Base::GetAssembler()->*f)(*reg1, *reg2, i, j, c);
174 template <typename Reg1, typename Reg2>
175 std::string RepeatTemplatedRRiiC(void (Ass::*f)(Reg1, Reg2, Imm, Imm, Cond),
176 const std::vector<Reg1*> reg1_registers
[all...] |
| /external/llvm/test/CodeGen/AMDGPU/ |
| pv-packing.ll | 6 define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 {
8 %0 = extractelement <4 x float> %reg1, i32 0
9 %1 = extractelement <4 x float> %reg1, i32 1
10 %2 = extractelement <4 x float> %reg1, i32 2
|
| /art/compiler/utils/ |
| assembler_test.h | 141 template <typename Reg1, typename Reg2, typename ImmType>
142 std::string RepeatTemplatedRegistersImmBits(void (Ass::*f)(Reg1, Reg2, ImmType),
144 const std::vector<Reg1*> reg1_registers,
146 std::string (AssemblerTest::*GetName1)(const Reg1&),
152 for (auto reg1 : reg1_registers) {
156 (assembler_.get()->*f)(*reg1, *reg2, new_imm);
159 std::string reg1_string = (this->*GetName1)(*reg1);
191 template <typename ImmType, typename Reg1, typename Reg2>
192 std::string RepeatTemplatedImmBitsRegisters(void (Ass::*f)(ImmType, Reg1, Reg2),
193 const std::vector<Reg1*> reg1_registers
[all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-microblaze.c | 894 unsigned reg1; local
939 op_end = parse_reg (op_end + 1, ®1); /* Get rd. */
943 reg1 = 0;
961 if (check_spl_reg (& reg1))
971 inst |= (reg1 << RD_LOW) & RD_MASK;
977 inst |= (reg1 << RD_LOW) & RD_MASK;
986 op_end = parse_reg (op_end + 1, ®1); /* Get rd. */
990 reg1 = 0;
1005 if (check_spl_reg (& reg1))
1053 count = 32 - reg1;
[all...] |
