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  /external/llvm/test/MC/ELF/
discriminator.s 59 # DWARF-DUMP: Address Line Column File ISA Discriminator Flags
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
mips32.s 50 # For a while break for the mips32 ISA interpreted a single argument
  /external/curl/tests/
sshhelp.pm 35 @ISA
63 @ISA = qw(Exporter);
  /external/llvm/test/MC/Mips/
set-push-pop-directives.s 20 .set mips32r6 # Test the Features option (ISA).
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/lns/
lns-common-1-alt.d 24 \[0x.*\] Set ISA to 1
  /toolchain/binutils/binutils-2.25/opcodes/
avr-dis.c 35 int isa; member in struct:avr_opcodes_s
39 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
40 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
344 if ((opcode->isa == AVR_ISA_TINY) && (info->mach != bfd_mach_avrtiny))
i370-opc.c 446 #define ISA I370_OPCODE_ESA390_SA
450 #define I390 IBF | IBS | ICK | ICM | IIR | IFX | IHX | IMI | IPC | IPL | IQR | IRP | ISA | ISG | ISR | ITR | I370_OPCODE_ESA390
    [all...]
  /external/clang/lib/CodeGen/
CGDeclCXX.cpp 291 InitSegAttr *ISA) {
295 PtrArray->setSection(ISA->getSection());
325 auto *ISA = D->getAttr<InitSegAttr>();
341 } else if (PerformInit && ISA) {
342 EmitPointerToInitFunc(D, Addr, Fn, ISA);
  /external/libdivsufsort/include/
divsufsort_private.h 200 trsort(saidx_t *ISA, saidx_t *SA, saidx_t n, saidx_t depth);
  /external/llvm/lib/Target/AMDGPU/
AMDGPUAsmPrinter.cpp 185 AMDGPU::IsaVersion ISA = STM.getIsaVersion();
186 TS->EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor, ISA.Stepping,
  /toolchain/binutils/binutils-2.25/gas/config/
tc-mips.c 197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
200 int isa; member in struct:mips_set_options
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64
1363 int isa; \/* ISA level. *\/ member in struct:mips_cpu_info
3239 int isa = mips_opts.isa; local
    [all...]
tc-avr.c 36 int isa; member in struct:avr_opcodes_s
40 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
41 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
57 int isa; member in struct:mcu_type_s
581 specified_mcu.isa |= mcu_types[i].isa;
600 specified_mcu.isa |= AVR_ISA_RMW;
970 && !(avr_mcu->isa & AVR_ISA_SRAM))
998 && !(avr_mcu->isa & AVR_ISA_MOVW))
    [all...]
  /prebuilts/go/darwin-x86/src/debug/dwarf/
line.go 101 // ISA is the instruction set architecture for these
102 // instructions. Possible ISA values should be defined by the
106 ISA int
443 r.state.ISA = int(r.buf.uint())
528 ISA: 0,
  /prebuilts/go/linux-x86/src/debug/dwarf/
line.go 101 // ISA is the instruction set architecture for these
102 // instructions. Possible ISA values should be defined by the
106 ISA int
443 r.state.ISA = int(r.buf.uint())
528 ISA: 0,
  /external/boringssl/src/crypto/modes/asm/
ghash-armv4.pl 258 bx lr @ interoperable with Thumb ISA:-)
336 bx lr @ interoperable with Thumb ISA:-)
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ppc/
vsx2.d 3 #name: VSX ISA 2.07 instructions
altivec2.d 3 #name: Altivec ISA 2.07 instructions
  /external/llvm/lib/Support/
Triple.cpp 278 unsigned ISA = ARM::parseArchISA(ArchName);
284 switch (ISA) {
298 switch (ISA) {
318 if (ISA == ARM::IK_THUMB &&
    [all...]
  /external/boringssl/linux-arm/crypto/bn/
armv4-mont.S 176 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
  /external/boringssl/src/crypto/bn/asm/
armv4-mont.pl 22 # The code is interoperable with Thumb ISA and is rather compact, less
258 bx lr @ interoperable with Thumb ISA:-)
  /external/autotest/client/tools/
boottool 1048 @Linux::Bootloader::Elilo::ISA = qw(Linux::Bootloader);
1251 @Linux::Bootloader::Grub::ISA = qw(Linux::Bootloader);
    [all...]
  /external/boringssl/linux-arm/crypto/aes/
aes-armv4.S 15 @ by gcc-3.4.1. This is thanks to unique feature of ARMv4 ISA, which
271 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
715 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
829 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
1046 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
  /external/boringssl/src/crypto/aes/asm/
aes-armv4.pl 15 # by gcc-3.4.1. This is thanks to unique feature of ARMv4 ISA, which
302 bx lr @ interoperable with Thumb ISA:-)
746 bx lr @ interoperable with Thumb ISA:-)
865 bx lr @ interoperable with Thumb ISA:-)
1082 bx lr @ interoperable with Thumb ISA:-)
    [all...]
  /external/boringssl/linux-arm/crypto/modes/
ghash-armv4.S 181 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
316 .word 0xe12fff1e @ interoperable with Thumb ISA:-)
  /external/boringssl/src/crypto/sha/asm/
sha1-armv4-large.pl 275 bx lr @ interoperable with Thumb ISA:-)

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