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  /external/llvm/test/MC/ARM/
eh-directive-vsave.s 50 .vsave {d0, d1, d2, d3, d4, d5, d6, d7}
51 vpush {d0, d1, d2, d3, d4, d5, d6, d7}
52 vpop {d0, d1, d2, d3, d4, d5, d6, d7}
63 .vsave {d2, d3, d4, d5, d6, d7}
64 vpush {d2, d3, d4, d5, d6, d7}
65 vpop {d2, d3, d4, d5, d6, d7}
single-precision-fp.s 7 vdiv.f64 d4, d5, d6
8 vmul.f64 d6, d7, d8
15 @ CHECK-ERRORS-NEXT: vdiv.f64 d4, d5, d6
17 @ CHECK-ERRORS-NEXT: vmul.f64 d6, d7, d8
22 vmls.f64 d8, d7, d6
26 vfms.f64 d4, d5, d6
32 @ CHECK-ERRORS-NEXT: vmls.f64 d8, d7, d6
40 @ CHECK-ERRORS-NEXT: vfms.f64 d4, d5, d6
60 vcmp.f64 d6, #0
70 @ CHECK-ERRORS-NEXT: vcmp.f64 d6, #
    [all...]
neont2-pairwise-encoding.s 20 vpaddl.u32 d6, d15
33 @ CHECK: vpaddl.u32 d6, d15 @ encoding: [0xb8,0xff,0x8f,0x62]
46 vpadal.u16 d12, d6
59 @ CHECK: vpadal.u16 d12, d6 @ encoding: [0xb4,0xff,0x86,0xc6]
89 vpmax.u8 d6, d23, d14
97 @ CHECK: vpmax.u8 d6, d23, d14 @ encoding: [0x07,0xff,0x8e,0x6a]
  /frameworks/av/media/libstagefright/codecs/aacenc/src/asm/ARMV7/
R4R8First_v7.s 47 VADD.S32 d6, d2, d3 @ r3 = buf[4] + buf[6]@i3 = buf[5] + buf[7]@
57 VADD.S32 d6, d10, d11 @ r2 = buf[12] + buf[14]@i2 = buf[13] + buf[15]@
90 VTRN.32 d6, d7
93 VSUB.S32 d15, d3, d6
95 VADD.S32 d19, d3, d6
137 VADD.S32 d6, d2, d3 @ r6 = buf[4] - buf[6]@ r7 = buf[5] - buf[7]@
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/arm/neon/
sixtappredict4x4_neon.asm 75 vext.8 d18, d6, d7, #5 ;construct src_ptr[3]
91 vzip.32 d6, d7 ;construct src_ptr[-2], and put 2-line data together
95 vmlal.u8 q7, d6, d0 ;+(src_ptr[-2] * vp8_filter[0])
105 vzip.32 d6, d7 ;put 2-line data in 1 register (src_ptr[2])
109 vmlsl.u8 q7, d6, d4 ;-(src_ptr[2] * vp8_filter[4])
119 vzip.32 d6, d7 ;put 2-line data in 1 register (src_ptr[1])
121 vmull.u8 q9, d6, d3 ;(src_ptr[1] * vp8_filter[3])
139 vext.8 d18, d6, d7, #5 ;construct src_ptr[3]
157 vzip.32 d6, d7 ;construct src_ptr[-2], and put 2-line data together
162 vmlal.u8 q7, d6, d0 ;+(src_ptr[-2] * vp8_filter[0]
    [all...]
shortidct4x4llm_neon.asm 59 ;d6 - c1:temp1
64 vqsub.s16 d10, d6, d9 ;c1
91 vqsub.s16 d10, d6, d9 ;c1
110 vld1.32 d6[0], [r1], r2
111 vld1.32 d6[1], [r1], r2
116 vaddw.u8 q1, q1, d6
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/m68k/
mcf-mac.d 129 1d6: aeee a0a9 000a macw %a1l,%a2u,%fp@\(10\)&,%sp
    [all...]
mcf-emac.d 262 3d6: aeee a0b9 000a macw %a1l,%a2u,%fp@\(10\)&,%sp,%acc2
    [all...]
mcf-emac.s     [all...]
  /external/libhevc/common/arm/
ihevc_itrans_recon_16x16.s 224 vld1.16 d6,[r0],r10
237 @d6= r1
242 vmull.s16 q12,d6,d0[1] @// y1 * cos1(part of b0)
243 vmull.s16 q13,d6,d0[3] @// y1 * cos3(part of b1)
244 vmull.s16 q14,d6,d1[1] @// y1 * sin3(part of b2)
245 vmull.s16 q15,d6,d1[3] @// y1 * sin1(part of b3)
307 vld1.16 d6,[r0],r10
317 vmlal.s16 q12,d6,d2[1] @// y1 * cos1(part of b0)
318 vmlsl.s16 q13,d6,d1[1] @// y1 * cos3(part of b1)
319 vmlsl.s16 q14,d6,d3[1] @// y1 * sin3(part of b2
    [all...]
ihevc_intra_pred_filters_chroma_mode_11_to_17.s 181 vrev64.16 d6,d6
189 vst1.8 d6,[r6]!
197 vld1.8 {d4,d5,d6},[r1]!
279 vmovn.s16 d6, q11
297 vand d6, d6, d29 @fract values in d1/ idx values in d0
311 vsub.s8 d7, d28, d6 @32-fract
322 vmlal.u8 q12, d13, d6 @mul (row 0)
332 vmlal.u8 q11, d17, d6 @mul (row 1
    [all...]
ihevc_intra_pred_chroma_planar.s 151 vdup.s8 d6, r9 @nt - 1 - row
182 vmlal.u8 q6, d6, d10 @(nt-1-row) * src[2nt+1+col]
192 vmlal.u8 q14,d6,d11
197 vsub.s8 d19, d6, d7 @[nt-1-row]--
217 vsub.s8 d6, d19, d7 @[nt-1-row]--
229 vmlal.u8 q11, d6, d10 @(nt-1-row) * src[2nt+1+col]
238 vmlal.u8 q10,d6,d11
239 vsub.s8 d19, d6, d7 @[nt-1-row]--
264 vsub.s8 d6, d19, d7 @[nt-1-row]--
307 vdup.s8 d6, r9 @nt - 1 - ro
    [all...]
ihevc_inter_pred_filters_luma_vert.s 165 vld1.u8 {d6},[r3],r2 @src_tmp3 = vld1_u8(pu1_src_tmp)@
170 vmlal.u8 q4,d6,d28 @mul_res1 = vmlal_u8(mul_res1, src_tmp3, coeffabs_6)@
189 vmlsl.u8 q5,d6,d27 @mul_res2 = vmlsl_u8(mul_res2, src_tmp3, coeffabs_5)@
207 vmlal.u8 q6,d6,d26
220 vmlal.u8 q7,d6,d25
227 vld1.u8 {d6},[r3],r2 @src_tmp3 = vld1_u8(pu1_src_tmp)@
258 vmlal.u8 q4,d6,d28 @mul_res1 = vmlal_u8(mul_res1, src_tmp3, coeffabs_6)@
281 vmlsl.u8 q5,d6,d27 @mul_res2 = vmlsl_u8(mul_res2, src_tmp3, coeffabs_5)@
303 vmlal.u8 q6,d6,d26
327 vmlal.u8 q7,d6,d2
    [all...]
  /external/boringssl/linux-arm/crypto/modes/
ghash-armv4.S 330 vld1.64 d6,[r1]
334 vshr.u64 d26,d6,#63
351 vld1.64 d6,[r0]!
382 vld1.64 d6,[r2]!
389 vmull.p8 q8, d16, d6 @ F = A1*B
390 vext.8 d0, d6, d6, #1 @ B1
393 vmull.p8 q9, d18, d6 @ H = A2*B
394 vext.8 d22, d6, d6, #2 @ B
    [all...]
  /external/libvpx/libvpx/vpx_dsp/arm/
loopfilter_8_neon.asm 54 vld1.u8 {d6}, [r2@64], r1 ; p0
112 vld1.u8 {d6}, [r2], r1
122 vtrn.32 d6, d18
125 vtrn.16 d4, d6
130 vtrn.8 d5, d6
181 ; d6 p0
198 vabd.u8 d21, d5, d6 ; m3 = abs(p1 - p0)
207 vabd.u8 d25, d6, d4 ; m7 = abs(p0 - p2)
215 vabd.u8 d24, d6, d7 ; m9 = abs(p0 - q0)
216 vabd.u8 d27, d3, d6 ; m10 = abs(p3 - p0
    [all...]
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/arm/neon/
vp9_loopfilter_neon.asm 58 vld1.u8 {d6}, [r3@64], r1 ; p0
71 vst1.u8 {d6}, [r2@64], r1 ; store oq0
118 vld1.u8 {d6}, [r2], r1
128 vtrn.32 d6, d18
131 vtrn.16 d4, d6
136 vtrn.8 d5, d6
145 vst4.8 {d4[0], d5[0], d6[0], d7[0]}, [r0], r1
146 vst4.8 {d4[1], d5[1], d6[1], d7[1]}, [r0], r1
147 vst4.8 {d4[2], d5[2], d6[2], d7[2]}, [r0], r1
148 vst4.8 {d4[3], d5[3], d6[3], d7[3]}, [r0], r
    [all...]
  /external/libavc/encoder/arm/
ime_distortion_metrics_a9q.s 99 vld1.8 {d6, d7}, [r1], r3
102 vabdl.u8 q0, d6, d4
111 vld1.8 {d6, d7}, [r1], r3
114 vabal.u8 q0, d6, d4
181 vld1.8 {d6, d7}, [r1], r3
185 vabdl.u8 q0, d6, d4
194 vld1.8 {d6, d7}, [r1], r3
197 vabal.u8 q0, d6, d4
264 vld1.8 {d6, d7}, [r1], r3
269 vabdl.u8 q0, d6, d
    [all...]
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/
psn.d 25 50: 09 f0 43 15 64 19 \[MMI\] lfetch.count.d6 \[r10\],63,-1024
50 d6: 00 00 00 02 00 00 nop.m 0x0
58 100: 0b 00 02 20 74 19 \[MMI\] lfetch.fault.d6 \[r16\];;
92 1b6: 00 ec 06 09 23 00 st1.d6 \[r65\]=r93
98 1d6: 00 e8 06 15 23 00 st2.d1 \[r65\]=r93
109 210: 08 00 76 83 8c 11 \[MMI\] st2.d6 \[r65\]=r93
125 266: 00 ec 06 29 23 00 st4.d6 \[r65\]=r93
142 2c0: 08 00 76 83 9c 11 \[MMI\] st8.d6 \[r65\]=r93
146 2d6: 00 e8 06 03 23 00 st16 \[r65\]=r93,ar.csd
160 320: 08 00 76 83 85 11 \[MMI\] st16.d6 \[r65\]=r93,ar.cs
    [all...]
  /external/libavc/common/arm/
ih264_inter_pred_filters_luma_vert_a9q.s 126 vaddl.u8 q6, d4, d6 @ temp1 = src[2_0] + src[3_0]
137 vaddl.u8 q6, d6, d8
156 vaddl.u8 q10, d6, d0
168 vaddl.u8 q7, d6, d4
188 vaddl.u8 q7, d8, d6 @ temp = src[0_0] + src[5_0]
214 vld1.u32 d6, [r0], r2
216 vaddl.u8 q8, d1, d6
223 vaddl.u8 q5, d3, d6
228 vaddl.u8 q7, d5, d6
264 vld1.u32 d6[0], [r0], r
    [all...]
  /external/libmpeg2/common/arm/
impeg2_idct.s 150 vld1.8 d6, [r2], r1
177 vaddw.u8 q10, q15, d6
182 vqmovun.s16 d6, q10
186 vst1.8 d6, [r3], r6
389 @// Row 1 First Half - D6 - y1
445 vld1.16 d6, [r0]!
447 vmull.s16 q12, d6, d0[1] @// y1 * cos1(part of b0)
449 vmull.s16 q13, d6, d0[3] @// y1 * cos3(part of b1)
451 vmull.s16 q14, d6, d1[1] @// y1 * sin3(part of b2)
453 vmull.s16 q15, d6, d1[3] @// y1 * sin1(part of b3
    [all...]
  /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/
armVCM4P10_DeblockingLuma_unsafe_s.S 47 VHADD.U8 d26,d24,d6
75 VADDL.U8 q11,d6,d9
80 VADDW.U8 q12,q12,d6
81 VADDL.U8 q13,d7,d6
105 VBIF d31,d6,d17
omxVCM4P10_FilterDeblockingChroma_VerEdge_I_s.S 51 VLD1.8 {d6},[r0],lr
57 VZIP.8 d6,d9
61 VZIP.16 d6,d4
63 VTRN.32 d7,d6
68 VABD.U8 d19,d6,d4
  /frameworks/rs/cpu_ref/
rsCpuIntrinsics_neon_Blend.S 91 vmull.u8 q3, d14, d6
117 vrshrn.u16 d6, q3, #8
175 vmull.u8 q0, d6, d16
177 vmull.u8 q1, d6, d18
179 vmull.u8 q2, d6, d20
181 vmull.u8 q3, d6, d22
207 vrshrn.u16 d6, q3, #8
220 vmull.u8 q3, d6, d22
246 vrshrn.u16 d6, q3, #8
275 vmull.u8 q8, d6, d1
    [all...]
  /system/core/libpixelflinger/
col32cb16blend_neon.S 52 vld4.8 {d0[], d2[], d4[], d6[]}, [r1] // load color into four registers
57 // d6 = 8 equal alpha values
62 vshr.u8 d7, d6, #7 // extract top bit of alpha
63 vaddl.u8 q3, d6, d7 // add top bit into alpha
  /external/boringssl/src/crypto/curve25519/asm/
x25519-asm-arm.S 68 vld1.8 {d6-d7},[r1]
70 vst1.8 {d6-d7},[r6,: 128]
184 vtrn.32 d4,d6
191 vtrn.32 d6,d0
196 vst1.8 d6,[r2,: 64]
263 vld1.8 {d6},[r7,: 64]
314 vld1.8 {d6-d7},[r4,: 128]!
336 vmlal.s32 q10,d6,d23
346 vmlal.s32 q1,d6,d1
349 vmull.s32 q14,d10,d6
    [all...]

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