| /external/llvm/test/MC/AArch64/ |
| elf-reloc-ldrlit.s | 6 ldrsw x9, some_label
|
| arm64-elf-relocs.s | 170 ldrsw x3, [x4, #:lo12:sym]
173 // CHECK: ldrsw x3, [x4, :lo12:sym]
180 ldrsw x3, [x4, #:dtprel_lo12_nc:sym]
183 // CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym]
191 ldrsw x3, [x4, :tprel_lo12_nc:sym]
194 // CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
|
| arm64-tls-relocs.s | 143 ldrsw x21, [x20, #:tprel_lo12_nc:var]
146 // CHECK: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
267 ldrsw x21, [x20, #:dtprel_lo12_nc:var]
270 // CHECK: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
|
| tls-relocs.s | 153 ldrsw x21, [x20, #:dtprel_lo12_nc:var]
157 // CHECK: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
355 ldrsw x21, [x20, #:tprel_lo12_nc:var]
359 // CHECK: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
|
| arm64-memory.s | 25 ldrsw x9, [sp, #512]
60 ; CHECK: ldrsw x9, [sp, #512] ; encoding: [0xe9,0x03,0x82,0xb9]
444 ldrsw x9, foo
449 ; CHECK: ldrsw x9, foo ; encoding: [0bAAA01001,A,A,0x98]
613 ldrsw x3, [x10, #10]
614 ldrsw x4, [x11, #-1]
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-extend.ll | 8 ; CHECK: ldrsw x0, [x[[REG1]], w0, sxtw #2]
|
| jump-table.ll | 28 ; CHECK-PIC: ldrsw [[DEST:x[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #2]
|
| aarch64-fix-cortex-a53-835769.ll | 163 ; CHECK: ldrsw
167 ; CHECK-NOWORKAROUND: ldrsw
183 ; CHECK: ldrsw
187 ; CHECK-NOWORKAROUND: ldrsw
202 ; CHECK: ldrsw
205 ; CHECK-NOWORKAROUND: ldrsw
|
| arm64-collect-loh.ll | 73 ; LDRSW supports loading from a literal.
81 ; CHECK-NEXT: ldrsw x0, {{\[}}[[LDRGOT_REG]]]
150 ; LDRSW supports loading from a literal.
158 ; CHECK-NEXT: ldrsw x0, {{\[}}[[ADDGOT_REG]], #16]
222 ; LDRSW supports loading from a literal.
228 ; CHECK-NEXT: ldrsw x0, {{\[}}[[ADRP_REG]], _InternalC@PAGEOFF]
|
| fast-isel-int-ext2.ll | 277 ; CHECK: ldrsw x0, [x0, x1]
427 ; CHECK: ldrsw x0, [x0, w1, sxtw]
|
| arm64-register-offset-addressing.ll | 95 ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw]
|
| fast-isel-int-ext.ll | 362 ; CHECK: ldrsw x0, [x0, x1]
482 ; CHECK: ldrsw x0, [x0, w1, sxtw]
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| programmer-friendly.d | 9 4: 98000241 ldrsw x1, 4c <\.text\+0x4c>
10 8: 98000007 ldrsw x7, 0 <\.text>
|
| ldst-reg-imm-post-ind.d | 188 2d0: b89007e7 ldrsw x7, \[sp\],#-256
189 2d4: b89557e7 ldrsw x7, \[sp\],#-171
190 2d8: b88007e7 ldrsw x7, \[sp\],#0
191 2dc: b88027e7 ldrsw x7, \[sp\],#2
192 2e0: b88047e7 ldrsw x7, \[sp\],#4
193 2e4: b88087e7 ldrsw x7, \[sp\],#8
194 2e8: b88107e7 ldrsw x7, \[sp\],#16
195 2ec: b88557e7 ldrsw x7, \[sp\],#85
196 2f0: b88ff7e7 ldrsw x7, \[sp\],#255
|
| ldst-reg-imm-pre-ind.d | 188 2d0: b8900fe7 ldrsw x7, \[sp,#-256\]!
189 2d4: b8955fe7 ldrsw x7, \[sp,#-171\]!
190 2d8: b8800fe7 ldrsw x7, \[sp,#0\]!
191 2dc: b8802fe7 ldrsw x7, \[sp,#2\]!
192 2e0: b8804fe7 ldrsw x7, \[sp,#4\]!
193 2e4: b8808fe7 ldrsw x7, \[sp,#8\]!
194 2e8: b8810fe7 ldrsw x7, \[sp,#16\]!
195 2ec: b8855fe7 ldrsw x7, \[sp,#85\]!
196 2f0: b88fffe7 ldrsw x7, \[sp,#255\]!
|
| programmer-friendly.s | 17 ldrsw x1, =0xdeadbeef
18 ldrsw x7, u16_lable + 4
|
| ldst-reg-uns-imm.d | 230 378: b98003e7 ldrsw x7, \[sp\]
231 37c: b98003e7 ldrsw x7, \[sp\]
233 384: b98007e7 ldrsw x7, \[sp,#4\]
234 388: b9800be7 ldrsw x7, \[sp,#8\]
235 38c: b98013e7 ldrsw x7, \[sp,#16\]
238 398: b9bfffe7 ldrsw x7, \[sp,#16380\]
|
| /external/valgrind/none/tests/arm64/ |
| memory.c | 178 TESTINST2_hide2("ldrsw x21, [x22, #24]", AREA_MID, x21,x22,0);
186 TESTINST2_hide2("ldrsw x21, [x22, #-24]!", AREA_MID, x21,x22,0);
192 TESTINST2_hide2("ldrsw x21, [x22], #-24", AREA_MID, x21,x22,0);
200 TESTINST2_hide2("ldrsw x21, [x22, #-24]", AREA_MID, x21,x22,0);
215 TESTINST3_hide2and3("ldrsw x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0);
216 TESTINST3_hide2and3("ldrsw x21, [x22,x23, lsl #2]", AREA_MID, 5, x21,x22,x23,0);
217 TESTINST3_hide2and3("ldrsw x21, [x22,w23,uxtw #0]", AREA_MID, 5, x21,x22,x23,0);
218 TESTINST3_hide2and3("ldrsw x21, [x22,w23,uxtw #2]", AREA_MID, 5, x21,x22,x23,0);
219 TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #0]", AREA_MID, -5ULL, x21,x22,x23,0);
220 TESTINST3_hide2and3("ldrsw x21, [x22,w23,sxtw #2]", AREA_MID, -5ULL, x21,x22,x23,0)
[all...] |
| /external/vixl/doc/ |
| changelog.md | 50 + Support `ldrsw` for literals.
|
| /external/v8/src/ic/arm64/ |
| ic-arm64.cc | 104 __ Ldrsw(scratch1, UntagSmiFieldMemOperand(scratch2, kDetailsOffset));
663 __ Ldrsw(x10, UntagSmiFieldMemOperand(elements, FixedArray::kLengthOffset));
708 __ Ldrsw(x10, UntagSmiFieldMemOperand(elements, FixedArray::kLengthOffset));
729 __ Ldrsw(x10, UntagSmiFieldMemOperand(receiver, JSArray::kLengthOffset));
[all...] |
| /external/v8/src/arm64/ |
| deoptimizer-arm64.cc | 239 __ Ldrsw(x1, MemOperand(x4, Deoptimizer::output_count_offset()));
|
| builtins-arm64.cc | [all...] |
| codegen-arm64.cc | 165 __ Ldrsw(length, UntagSmiFieldMemOperand(elements,
273 __ Ldrsw(length, UntagSmiFieldMemOperand(elements,
|
| /external/v8/test/cctest/ |
| test-disasm-arm64.cc | [all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-memory.txt | 28 # CHECK: ldrsw x0, [x1, x0, lsl #2]
35 # CHECK: ldrsw x9, [sp, #512]
544 # CHECK: ldrsw x0, [x1, x0, lsl #2]
|
