| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/rx/ |
| max.sm | 2 max {reg1},{reg}
|
| /external/vulkan-validation-layers/libs/glm/detail/ |
| intrinsic_integer.inl | 40 __m128i Reg1;
43 // REG1 = x;
45 //Reg1 = _mm_unpacklo_epi64(x, y);
46 Reg1 = x;
48 //REG1 = ((REG1 << 16) | REG1) & glm::uint64(0x0000FFFF0000FFFF);
50 Reg2 = _mm_slli_si128(Reg1, 2);
51 Reg1 = _mm_or_si128(Reg2, Reg1);
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| x86-64-specific-reg.s | 5 .irp reg1, ax, cx, dx, bx, sp, bp, si, di
6 lodsb %ds:(%r\reg1)
8 stosb %es:(%r\reg1)
10 scasb %es:(%r\reg1)
12 insb %dx, %es:(%r\reg1)
14 outsb %ds:(%r\reg1), %dx
16 xlatb %ds:(%r\reg1)
18 movsb %ds:(%r\reg1), %es:(%rdi)
19 movsb %ds:(%rsi), %es:(%r\reg1)
21 cmpsb %es:(%r\reg1), %ds:(%rsi
[all...] |
| /external/llvm/test/FileCheck/ |
| check-dag.txt | 15 ; CHECK-DAG: add [[REG1:r[0-9]+]], r1, r2
17 ; CHECK: mul r5, [[REG1]], [[REG2]]
19 ; CHECK-DAG: mul [[REG1:r[0-9]+]], r1, r2
21 ; CHECK: add r5, [[REG1]], [[REG2]]
23 ; CHECK-DAG: add [[REG1:r[0-9]+]], r1, r2
26 ; CHECK-DAG: mul r5, [[REG1]], [[REG2]]
|
| check-dag-multi-prefix.txt | 15 ; B-DAG: add [[REG1:r[0-9]+]], r1, r2
17 ; B: mul r5, [[REG1]], [[REG2]]
19 ; A-DAG: mul [[REG1:r[0-9]+]], r1, r2
21 ; A: add r5, [[REG1]], [[REG2]]
23 ; B-DAG: add [[REG1:r[0-9]+]], r1, r2
26 ; B-DAG: mul r5, [[REG1]], [[REG2]]
|
| check-dag-xfails.txt | 15 ; X1-DAG: add [[REG1:r[0-9]+]], r1, r2
17 ; X1: mul r5, [[REG1]], [[REG2]]
27 ; X2-DAG: mul [[REG1:r[0-9]+]], r1, r2
29 ; X2: add r5, [[REG1]], [[REG2]]
39 ; X3-DAG: add [[REG1:r[0-9]+]], r1, r2
41 ; X3-DAG: mul r5, [[REG1]], [[REG2]]
52 ; X4-DAG: add [[REG1:r[0-9]+]], r1, r2
55 ; X4-DAG: mul r5, [[REG1]], [[REG2]]
66 ; X5-DAG: add [[REG1:r[0-9]+]], r1, r2
69 ; X5-DAG: mul r5, [[REG1]], [[REG2]
[all...] |
| var-ref-same-line.txt | 10 ; CHECK: op3 [[REG1:r[0-9]+]], [[REG2:r[0-9]+]], [[REG1]], [[REG2]]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| constants-i64.ll | 11 ; CHECK: lis [[REG1:[0-9]+]], -1
12 ; CHECK: rldicr 3, [[REG1]], 48, 63
22 ; CHECK: lis [[REG1:[0-9]+]], -81
23 ; CHECK: rldicr 3, [[REG1]], 48, 63
33 ; CHECK: li [[REG1:[0-9]+]], -1
34 ; CHECK: sldi 3, [[REG1]], 36
44 ; CHECK: li [[REG1:[0-9]+]], -337
45 ; CHECK: sldi 3, [[REG1]], 30
55 ; CHECK: lis [[REG1:[0-9]+]], -4096
56 ; CHECK: rldicr 3, [[REG1]], 36, 6
[all...] |
| fp-to-int-to-fp.ll | 14 ; FPCVT: fctidz [[REG1:[0-9]+]], 1
15 ; FPCVT: fcfids 1, [[REG1]]
19 ; PPC64: fctidz [[REG1:[0-9]+]], 1
20 ; PPC64: fcfid [[REG2:[0-9]+]], [[REG1]]
33 ; FPCVT: fctidz [[REG1:[0-9]+]], 1
34 ; FPCVT: fcfid 1, [[REG1]]
38 ; PPC64: fctidz [[REG1:[0-9]+]], 1
39 ; PPC64: fcfid 1, [[REG1]]
51 ; FPCVT: fctiduz [[REG1:[0-9]+]], 1
52 ; FPCVT: fcfidus 1, [[REG1]]
[all...] |
| tls.ll | 13 ;OPT0: addis [[REG1:[0-9]+]], 13, a@tprel@ha
15 ;OPT0-NEXT: addi [[REG1]], [[REG1]], a@tprel@l
16 ;OPT0: stw [[REG2]], 0([[REG1]])
17 ;OPT1: addis [[REG1:[0-9]+]], 13, a@tprel@ha
19 ;OPT1-NEXT: stw [[REG2]], a@tprel@l([[REG1]])
38 ; OPT1: addis [[REG1:[0-9]+]], 2, a2@got@tprel@ha
39 ; OPT1: ld [[REG2:[0-9]+]], a2@got@tprel@l([[REG1]])
43 ;OPT0-PPC32: li [[REG1:[0-9]+]], _GLOBAL_OFFSET_TABLE_@l
44 ;OPT0-PPC32: addis [[REG1]], [[REG1]], _GLOBAL_OFFSET_TABLE_@h
[all...] |
| no-extra-fp-conv-ldst.ll | 13 ; CHECK: lfd [[REG1:[0-9]+]], 0(3)
14 ; CHECK: fcfid 1, [[REG1]]
26 ; CHECK: lfiwax [[REG1:[0-9]+]], 0, 3
27 ; CHECK: fcfid 1, [[REG1]]
40 ; CHECK-DAG: addi [[REG1:[0-9]+]], 1,
41 ; CHECK: stfiwx [[REG2]], 0, [[REG1]]
42 ; CHECK: lfiwax [[REG3:[0-9]+]], 0, [[REG1]]
56 ; CHECK-DAG: addi [[REG1:[0-9]+]], 1,
57 ; CHECK: stfiwx [[REG2]], 0, [[REG1]]
58 ; CHECK: lfiwax [[REG3:[0-9]+]], 0, [[REG1]]
[all...] |
| vaddsplat.ll | 20 ; CHECK: vspltisw [[REG1:[0-9]+]], 9
21 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]]
31 ; CHECK: vspltisw [[REG1:[0-9]+]], -14
32 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]]
42 ; CHECK: vspltish [[REG1:[0-9]+]], 15
43 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]]
53 ; CHECK: vspltish [[REG1:[0-9]+]], -1
[all...] |
| i1-ext-fold.ll | 15 ; CHECK-DAG: li [[REG1:[0-9]+]], 0
17 ; CHECK: isel 3, [[REG2]], [[REG1]],
32 ; CHECK-DAG: li [[REG1:[0-9]+]], 5
34 ; CHECK: isel 3, [[REG2]], [[REG1]],
48 ; CHECK-DAG: li [[REG1:[0-9]+]], 16
49 ; CHECK: isel 3, 0, [[REG1]],
|
| bperm.ll | 12 ; CHECK: rlwinm [[REG1:[0-9]+]], 3, 8, 0, 31
13 ; CHECK: rlwimi [[REG1]], 3, 24, 16, 23
14 ; CHECK: rlwimi [[REG1]], 3, 24, 0, 7
15 ; CHECK: mr 3, [[REG1]]
25 ; CHECK-DAG: rotldi [[REG1:[0-9]+]], 3, 16
28 ; CHECK-DAG: rldimi [[REG2]], [[REG1]], 8, 48
48 ; CHECK-DAG: li [[REG1:[0-9]+]], 11375
50 ; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 19
62 ; CHECK-DAG: lis [[REG1:[0-9]+]], 474
64 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 364
[all...] |
| fp-to-int-ext.ll | 14 ; CHECK: lfiwax [[REG1:[0-9]+]], 0, 3
15 ; CHECK: fcfid 1, [[REG1]]
27 ; CHECK: lfiwzx [[REG1:[0-9]+]], 0, 3
28 ; CHECK: fcfid 1, [[REG1]]
41 ; CHECK-DAG: lwz [[REG1:[0-9]+]], 0(3)
43 ; CHECK-DAG: addi [[REG2:[0-9]+]], [[REG1]], 8
59 ; CHECK-DAG: lwz [[REG1:[0-9]+]], 0(3)
61 ; CHECK-DAG: addi [[REG2:[0-9]+]], [[REG1]], 8
|
| sdiv-pow2.ll | 13 ; CHECK: srawi [[REG1:[0-9]+]], 3, 3
14 ; CHECK: addze [[REG2:[0-9]+]], [[REG1]]
26 ; CHECK: sradi [[REG1:[0-9]+]], 3, 3
27 ; CHECK: addze 3, [[REG1]]
42 ; CHECK: srawi [[REG1:[0-9]+]], 3, 3
43 ; CHECK: addze [[REG2:[0-9]+]], [[REG1]]
56 ; CHECK: sradi [[REG1:[0-9]+]], 3, 3
57 ; CHECK: addze [[REG2:[0-9]+]], [[REG1]]
|
| /external/vulkan-validation-layers/libs/glm/gtx/ |
| bit.inl | 363 glm::uint16 REG1(x);
366 REG1 = ((REG1 << 4) | REG1) & glm::uint16(0x0F0F);
369 REG1 = ((REG1 << 2) | REG1) & glm::uint16(0x3333);
372 REG1 = ((REG1 << 1) | REG1) & glm::uint16(0x5555)
[all...] |
| /external/libavc/common/armv8/ |
| ih264_neon_macros.s | 36 .macro swp reg1, reg2
37 eor \reg1, \reg1, \reg2
38 eor \reg2, \reg1, \reg2
39 eor \reg1, \reg1, \reg2
|
| /external/libmpeg2/common/armv8/ |
| impeg2_neon_macros.s | 53 .macro swp reg1, reg2
54 eor \reg1, \reg1, \reg2
55 eor \reg2, \reg1, \reg2
56 eor \reg1, \reg1, \reg2
|
| /external/llvm/test/CodeGen/AArch64/ |
| aarch64-be-bv.ll | 7 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
9 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
10 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
19 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
21 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
22 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
31 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
33 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8
[all...] |
| fast-isel-sdiv.ll | 13 ; CHECK: add [[REG1:w[0-9]+]], w0, #7
15 ; CHECK-NEXT: csel [[REG2:w[0-9]+]], [[REG1]], w0, lt
23 ; CHECK: add [[REG1:w[0-9]+]], w0, #7
25 ; CHECK-NEXT: csel [[REG2:w[0-9]+]], [[REG1]], w0, lt
40 ; CHECK: add [[REG1:x[0-9]+]], x0, #15
42 ; CHECK-NEXT: csel [[REG2:x[0-9]+]], [[REG1]], x0, lt
50 ; CHECK: add [[REG1:x[0-9]+]], x0, #15
52 ; CHECK-NEXT: csel [[REG2:x[0-9]+]], [[REG1]], x0, lt
|
| /external/libvpx/libvpx/vpx_dsp/mips/ |
| idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
50 DOTP_CONST_PAIR(reg1, reg7, cospi_28_64, cospi_4_64, reg1, reg7);
52 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0);
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
69 DOTP_CONST_PAIR(reg6, reg1, cospi_6_64, cospi_26_64, reg6, reg1);
75 reg2 = reg1 + reg5;
76 reg1 = reg1 - reg5
128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
359 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
439 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
[all...] |
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| simplestorei.ll | 13 ; CHECK: addiu $[[REG1:[0-9]+]], $zero, 32767
15 ; CHECK: sw $[[REG1]], 0($[[REG2]])
25 ; CHECK: lui $[[REG1:[0-9]+]], 65535
26 ; CHECK: ori $[[REG2:[0-9]+]], $[[REG1]], 32768
37 ; CHECK: ori $[[REG1:[0-9]+]], $zero, 65535
39 ; CHECK: sw $[[REG1]], 0($[[REG2]])
48 ; CHECK: lui $[[REG1:[0-9]+]], 15
50 ; CHECK: sw $[[REG1]], 0($[[REG2]])
59 ; CHECK: lui $[[REG1:[0-9]+]], 10
60 ; CHECK: ori $[[REG1]], $[[REG1]], 6420
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| atomic-64bit.ll | 9 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
10 ; CHECK-LE: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
13 ; CHECK-BE: adc [[REG3:(r[0-9]?[02468])]], [[REG1]]
21 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
22 ; CHECK-THUMB-LE: adds.w [[REG3:[a-z0-9]+]], [[REG1]]
25 ; CHECK-THUMB-BE: adc.w [[REG3:[a-z0-9]+]], [[REG1]]
38 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
39 ; CHECK-LE: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
42 ; CHECK-BE: sbc [[REG3:(r[0-9]?[02468])]], [[REG1]]
50 ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]
[all...] |
| /external/llvm/test/CodeGen/Thumb/ |
| 2012-04-26-M0ISelBug.ll | 7 ; CHECK: asrs [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], #31
8 ; CHECK: eors [[REG2]], [[REG1]]
|
