| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIGenRegisterInfo.pl | 47 class SI_64 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
52 class SI_128 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
57 class SI_256 <string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
75 class SGPR_64 <bits<8> num, string name, list<Register> subregs> :
76 SI_64 <name, subregs>;
78 class VGPR_64 <bits<9> num, string name, list<Register> subregs> :
79 SI_64 <name, subregs>;
[all...] |
| R600GenRegisterInfo.pl | 31 class R600Reg_128<string n, list<Register> subregs> : RegisterWithSubRegs<n, subregs> {
|
| /external/llvm/lib/CodeGen/ |
| LiveVariables.cpp | 197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
198 unsigned SubReg = *SubRegs;
220 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true);
221 SubRegs.isValid(); ++SubRegs)
222 PartDefRegs.insert(*SubRegs);
251 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
[all...] |
| ScheduleDAGInstrs.cpp | [all...] |
| MachineVerifier.cpp | 94 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
95 RV.push_back(*SubRegs);
475 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
477 // assert(regsReserved.test(*SubRegs) && "Non-reserved sub-register");
478 regsReserved.set(*SubRegs);
699 for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true)
[all...] |
| MachineInstrBundle.cpp | 186 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
187 unsigned SubReg = *SubRegs;
|
| CriticalAntiDepBreaker.cpp | 217 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
218 SubRegs.isValid(); ++SubRegs) {
219 KeepRegs.set(*SubRegs);
229 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
230 SubRegs.isValid(); ++SubRegs)
231 KeepRegs.set(*SubRegs);
271 // For the reg itself and all subregs: update the def to current;
|
| RegisterScavenging.cpp | 217 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
218 if (isRegUsed(*SubRegs)) {
|
| AggressiveAntiDepBreaker.cpp | 244 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
245 SubRegs.isValid(); ++SubRegs)
246 PassthruRegs.insert(*SubRegs);
318 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
319 unsigned SubregReg = *SubRegs;
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LivePhysRegs.h | 77 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
78 SubRegs.isValid(); ++SubRegs)
79 LiveRegs.insert(*SubRegs);
87 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
88 SubRegs.isValid(); ++SubRegs)
89 LiveRegs.erase(*SubRegs);
|
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPURegisterInfo.cpp | 46 static const unsigned SubRegs[] = {
53 assert(Channel < array_lengthof(SubRegs));
54 return SubRegs[Channel];
|
| R600RegisterInfo.td | 19 class R600Reg_128<string n, list<Register> subregs, bits<16> encoding> :
20 RegisterWithSubRegs<n, subregs> {
28 class R600Reg_64<string n, list<Register> subregs, bits<16> encoding> :
29 RegisterWithSubRegs<n, subregs> {
|
| SIFoldOperands.cpp | 207 // FIXME: Fold operands with subregs.
337 // FIXME: Fold operands with subregs.
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.td | 23 class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs,
25 RegisterWithSubRegs<n, subregs> {
45 class Rd<bits<5> num, string n, list<Register> subregs> :
46 HexagonDoubleReg<num, n, subregs> {
48 let SubRegs = subregs;
70 class Rcc<bits<5> num, string n, list<Register> subregs,
72 HexagonDoubleReg<num, n, subregs, alt> {
74 let SubRegs = subregs;
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-dead-register-def-bug.ll | 5 ; with dead defs, but live implicit-defs of subregs:
|
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.td | 36 class Rdi<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
37 let SubRegs = subregs;
45 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
46 let SubRegs = subregs;
52 class Rq<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
53 let SubRegs = subregs;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.td | 38 let SubRegs = [SubReg];
55 let SubRegs = [SubReg];
70 let SubRegs = [SubReg];
78 let SubRegs = [SubReg];
87 let SubRegs = [SubReg];
92 class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
94 let SubRegs = subregs;
|
| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.td | 35 class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
36 : RegisterWithSubRegs<n, subregs> {
45 class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
46 : MipsRegWithSubRegs<Enc, n, subregs> {
54 class AFPR<bits<16> Enc, string n, list<Register> subregs>
55 : MipsRegWithSubRegs<Enc, n, subregs> {
60 class AFPR64<bits<16> Enc, string n, list<Register> subregs>
61 : MipsRegWithSubRegs<Enc, n, subregs> {
67 class AFPR128<bits<16> Enc, string n, list<Register> subregs>
68 : MipsRegWithSubRegs<Enc, n, subregs> {
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 119 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
123 "SubRegs and SubRegIndices must have the same size");
131 // covered-by-subregs super-registers where it appears as the first explicit
204 for (SubRegMap::const_iterator I = SubRegs.begin(), E = SubRegs.end();
218 return SubRegs;
223 // First insert the explicit subregs and make sure they are fully indexed.
227 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
235 // Keep track of inherited subregs and how they can be reached.
238 // Clone inherited subregs and place duplicate entries in Orphans
[all...] |
| /external/llvm/lib/Target/AVR/ |
| AVRRegisterInfo.td | 17 list<Register> subregs = [],
19 : RegisterWithSubRegs<name, subregs>
25 let SubRegs = subregs;
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.td | 19 class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs>
20 : RegisterWithSubRegs<n, subregs> {
|
| /external/llvm/lib/Target/ARM/ |
| ARMRegisterInfo.td | 15 class ARMReg<bits<16> Enc, string n, list<Register> subregs = []> : Register<n> {
18 let SubRegs = subregs;
303 // 32-bit SPR subregs).
320 // Subset of QPR that have 32-bit SPR subregs.
324 // Subset of QPR that have DPR_8 and SPR_8 subregs.
|
| /external/llvm/include/llvm/Target/ |
| Target.td | 48 // in the SubRegs field of a Register definition. For example:
90 // SubRegs - A list of registers that are parts of this register. Note these
92 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
94 list<Register> SubRegs = [];
96 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
98 // SubRegs.
132 // List "subregs" specifies which registers are sub-registers to this one. This
133 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
136 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
137 let SubRegs = subregs
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.td | 18 class SystemZRegWithSubregs<string n, list<Register> subregs>
19 : RegisterWithSubRegs<n, subregs> {
120 // Not used directly, but needs to exist for ADDR32 and ADDR64 subregs
|
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 99 /// register. The SubRegs field is a zero terminated array of registers that
107 uint32_t SubRegs; // Sub-register set, described above
111 // sub-register in SubRegs.
458 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
|
