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    Searched full:v_add_i32 (Results 1 - 13 of 13) sorted by null

  /external/llvm/test/CodeGen/AMDGPU/
add_i64.ll 7 ; SI: v_add_i32
22 ; SI: v_add_i32
35 ; SI: v_add_i32
57 ; SI: v_add_i32
59 ; SI: v_add_i32
sminmax.ll 19 ; GCN: v_add_i32
55 ; GCN: v_add_i32
56 ; GCN: v_add_i32
110 ; GCN: v_add_i32
111 ; GCN: v_add_i32
112 ; GCN: v_add_i32
113 ; GCN: v_add_i32
move-addr64-rsrc-dead-subreg-writes.ll 6 ; FIXME: We should be able to use the SGPR directly as src0 to v_add_i32
sdiv.ll 40 ; SI: v_add_i32
43 ; SI: v_add_i32
uaddo.ll 40 ; SI: v_add_i32
71 ; SI: v_add_i32
saddo.ll 52 ; SI: v_add_i32
llvm.AMDGPU.bfe.u32.ll 77 ; SI: v_add_i32
92 ; SI: v_add_i32
107 ; SI: v_add_i32
121 ; SI: v_add_i32
136 ; SI: v_add_i32
151 ; SI: v_add_i32
split-scalar-i64-add.ll 36 ; SI: v_add_i32
add.ll 140 ; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they
  /external/llvm/test/MC/AMDGPU/
out-of-range-registers.s 10 v_add_i32 v256, v0, v1 label
13 v_add_i32 v257, v0, v1 label
vop2.s 256 v_add_i32 v1, vcc, v2, v3 label
260 v_add_i32 v1, s[0:1], v2, v3 label
  /external/mesa3d/src/gallium/drivers/radeon/
SIInstructions.td     [all...]
  /external/llvm/lib/Target/AMDGPU/
SIInstructions.td     [all...]

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