1 ; RUN: llc -march=amdgcn -mcpu=kaveri -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefix=GCN %s 2 3 ; Check that when mubuf addr64 instruction is handled in moveToVALU 4 ; from the pointer, dead register writes are not emitted. 5 6 ; FIXME: We should be able to use the SGPR directly as src0 to v_add_i32 7 8 ; GCN-LABEL: {{^}}clobber_vgpr_pair_pointer_add: 9 ; GCN: s_load_dwordx2 s{{\[}}[[ARG1LO:[0-9]+]]:[[ARG1HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}} 10 ; GCN: buffer_load_dwordx2 v{{\[}}[[LDPTRLO:[0-9]+]]:[[LDPTRHI:[0-9]+]]{{\]}} 11 12 ; GCN-NOT: v_mov_b32 13 ; GCN: v_mov_b32_e32 v[[VARG1LO:[0-9]+]], s[[ARG1LO]] 14 ; GCN-NEXT: v_mov_b32_e32 v[[VARG1HI:[0-9]+]], s[[ARG1HI]] 15 ; GCN-NOT: v_mov_b32 16 17 ; GCN: v_add_i32_e32 v[[PTRLO:[0-9]+]], vcc, v[[LDPTRLO]], v[[VARG1LO]] 18 ; GCN: v_addc_u32_e32 v[[PTRHI:[0-9]+]], vcc, v[[LDPTRHI]], v[[VARG1HI]] 19 ; GCN: buffer_load_ubyte v{{[0-9]+}}, v{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, 20 21 define void @clobber_vgpr_pair_pointer_add(i64 %arg1, i8 addrspace(1)* addrspace(1)* %ptrarg, i32 %arg3) #0 { 22 bb: 23 %tmp = icmp sgt i32 %arg3, 0 24 br i1 %tmp, label %bb4, label %bb17 25 26 bb4: 27 %tmp14 = load volatile i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* %ptrarg 28 %tmp15 = getelementptr inbounds i8, i8 addrspace(1)* %tmp14, i64 %arg1 29 %tmp16 = load volatile i8, i8 addrspace(1)* %tmp15 30 br label %bb17 31 32 bb17: 33 ret void 34 } 35 36 attributes #0 = { nounwind } 37
