1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __RADEON_DRM_H__ 20 #define __RADEON_DRM_H__ 21 #include "drm.h" 22 #ifndef __RADEON_SAREA_DEFINES__ 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #define __RADEON_SAREA_DEFINES__ 25 #define RADEON_UPLOAD_CONTEXT 0x00000001 26 #define RADEON_UPLOAD_VERTFMT 0x00000002 27 #define RADEON_UPLOAD_LINE 0x00000004 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define RADEON_UPLOAD_BUMPMAP 0x00000008 30 #define RADEON_UPLOAD_MASKS 0x00000010 31 #define RADEON_UPLOAD_VIEWPORT 0x00000020 32 #define RADEON_UPLOAD_SETUP 0x00000040 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define RADEON_UPLOAD_TCL 0x00000080 35 #define RADEON_UPLOAD_MISC 0x00000100 36 #define RADEON_UPLOAD_TEX0 0x00000200 37 #define RADEON_UPLOAD_TEX1 0x00000400 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define RADEON_UPLOAD_TEX2 0x00000800 40 #define RADEON_UPLOAD_TEX0IMAGES 0x00001000 41 #define RADEON_UPLOAD_TEX1IMAGES 0x00002000 42 #define RADEON_UPLOAD_TEX2IMAGES 0x00004000 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 #define RADEON_UPLOAD_CLIPRECTS 0x00008000 45 #define RADEON_REQUIRE_QUIESCENCE 0x00010000 46 #define RADEON_UPLOAD_ZBIAS 0x00020000 47 #define RADEON_UPLOAD_ALL 0x003effff 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff 50 #define RADEON_EMIT_PP_MISC 0 51 #define RADEON_EMIT_PP_CNTL 1 52 #define RADEON_EMIT_RB3D_COLORPITCH 2 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 #define RADEON_EMIT_RE_LINE_PATTERN 3 55 #define RADEON_EMIT_SE_LINE_WIDTH 4 56 #define RADEON_EMIT_PP_LUM_MATRIX 5 57 #define RADEON_EMIT_PP_ROT_MATRIX_0 6 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 #define RADEON_EMIT_RB3D_STENCILREFMASK 7 60 #define RADEON_EMIT_SE_VPORT_XSCALE 8 61 #define RADEON_EMIT_SE_CNTL 9 62 #define RADEON_EMIT_SE_CNTL_STATUS 10 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 #define RADEON_EMIT_RE_MISC 11 65 #define RADEON_EMIT_PP_TXFILTER_0 12 66 #define RADEON_EMIT_PP_BORDER_COLOR_0 13 67 #define RADEON_EMIT_PP_TXFILTER_1 14 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 #define RADEON_EMIT_PP_BORDER_COLOR_1 15 70 #define RADEON_EMIT_PP_TXFILTER_2 16 71 #define RADEON_EMIT_PP_BORDER_COLOR_2 17 72 #define RADEON_EMIT_SE_ZBIAS_FACTOR 18 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 75 #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 76 #define R200_EMIT_PP_TXCBLEND_0 21 77 #define R200_EMIT_PP_TXCBLEND_1 22 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 #define R200_EMIT_PP_TXCBLEND_2 23 80 #define R200_EMIT_PP_TXCBLEND_3 24 81 #define R200_EMIT_PP_TXCBLEND_4 25 82 #define R200_EMIT_PP_TXCBLEND_5 26 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 #define R200_EMIT_PP_TXCBLEND_6 27 85 #define R200_EMIT_PP_TXCBLEND_7 28 86 #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 87 #define R200_EMIT_TFACTOR_0 30 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 #define R200_EMIT_VTX_FMT_0 31 90 #define R200_EMIT_VAP_CTL 32 91 #define R200_EMIT_MATRIX_SELECT_0 33 92 #define R200_EMIT_TEX_PROC_CTL_2 34 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 95 #define R200_EMIT_PP_TXFILTER_0 36 96 #define R200_EMIT_PP_TXFILTER_1 37 97 #define R200_EMIT_PP_TXFILTER_2 38 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 #define R200_EMIT_PP_TXFILTER_3 39 100 #define R200_EMIT_PP_TXFILTER_4 40 101 #define R200_EMIT_PP_TXFILTER_5 41 102 #define R200_EMIT_PP_TXOFFSET_0 42 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 #define R200_EMIT_PP_TXOFFSET_1 43 105 #define R200_EMIT_PP_TXOFFSET_2 44 106 #define R200_EMIT_PP_TXOFFSET_3 45 107 #define R200_EMIT_PP_TXOFFSET_4 46 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 #define R200_EMIT_PP_TXOFFSET_5 47 110 #define R200_EMIT_VTE_CNTL 48 111 #define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 112 #define R200_EMIT_PP_TAM_DEBUG3 50 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 #define R200_EMIT_PP_CNTL_X 51 115 #define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 116 #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 117 #define R200_EMIT_RE_SCISSOR_TL_0 54 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 #define R200_EMIT_RE_SCISSOR_TL_1 55 120 #define R200_EMIT_RE_SCISSOR_TL_2 56 121 #define R200_EMIT_SE_VAP_CNTL_STATUS 57 122 #define R200_EMIT_SE_VTX_STATE_CNTL 58 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 #define R200_EMIT_RE_POINTSIZE 59 125 #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 126 #define R200_EMIT_PP_CUBIC_FACES_0 61 127 #define R200_EMIT_PP_CUBIC_OFFSETS_0 62 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 #define R200_EMIT_PP_CUBIC_FACES_1 63 130 #define R200_EMIT_PP_CUBIC_OFFSETS_1 64 131 #define R200_EMIT_PP_CUBIC_FACES_2 65 132 #define R200_EMIT_PP_CUBIC_OFFSETS_2 66 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 #define R200_EMIT_PP_CUBIC_FACES_3 67 135 #define R200_EMIT_PP_CUBIC_OFFSETS_3 68 136 #define R200_EMIT_PP_CUBIC_FACES_4 69 137 #define R200_EMIT_PP_CUBIC_OFFSETS_4 70 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 #define R200_EMIT_PP_CUBIC_FACES_5 71 140 #define R200_EMIT_PP_CUBIC_OFFSETS_5 72 141 #define RADEON_EMIT_PP_TEX_SIZE_0 73 142 #define RADEON_EMIT_PP_TEX_SIZE_1 74 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 #define RADEON_EMIT_PP_TEX_SIZE_2 75 145 #define R200_EMIT_RB3D_BLENDCOLOR 76 146 #define R200_EMIT_TCL_POINT_SPRITE_CNTL 77 147 #define RADEON_EMIT_PP_CUBIC_FACES_0 78 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79 150 #define RADEON_EMIT_PP_CUBIC_FACES_1 80 151 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81 152 #define RADEON_EMIT_PP_CUBIC_FACES_2 82 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83 155 #define R200_EMIT_PP_TRI_PERF_CNTL 84 156 #define R200_EMIT_PP_AFS_0 85 157 #define R200_EMIT_PP_AFS_1 86 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 #define R200_EMIT_ATF_TFACTOR 87 160 #define R200_EMIT_PP_TXCTLALL_0 88 161 #define R200_EMIT_PP_TXCTLALL_1 89 162 #define R200_EMIT_PP_TXCTLALL_2 90 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 #define R200_EMIT_PP_TXCTLALL_3 91 165 #define R200_EMIT_PP_TXCTLALL_4 92 166 #define R200_EMIT_PP_TXCTLALL_5 93 167 #define R200_EMIT_VAP_PVS_CNTL 94 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 #define RADEON_MAX_STATE_PACKETS 95 170 #define RADEON_CMD_PACKET 1 171 #define RADEON_CMD_SCALARS 2 172 #define RADEON_CMD_VECTORS 3 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 #define RADEON_CMD_DMA_DISCARD 4 175 #define RADEON_CMD_PACKET3 5 176 #define RADEON_CMD_PACKET3_CLIP 6 177 #define RADEON_CMD_SCALARS2 7 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 #define RADEON_CMD_WAIT 8 180 #define RADEON_CMD_VECLINEAR 9 181 typedef union { 182 int i; 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 struct { 185 unsigned char cmd_type, pad0, pad1, pad2; 186 } header; 187 struct { 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 unsigned char cmd_type, packet_id, pad0, pad1; 190 } packet; 191 struct { 192 unsigned char cmd_type, offset, stride, count; 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 } scalars; 195 struct { 196 unsigned char cmd_type, offset, stride, count; 197 } vectors; 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 struct { 200 unsigned char cmd_type, addr_lo, addr_hi, count; 201 } veclinear; 202 struct { 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 unsigned char cmd_type, buf_idx, pad0, pad1; 205 } dma; 206 struct { 207 unsigned char cmd_type, flags, pad0, pad1; 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 } wait; 210 } drm_radeon_cmd_header_t; 211 #define RADEON_WAIT_2D 0x1 212 #define RADEON_WAIT_3D 0x2 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 #define R300_CMD_PACKET3_CLEAR 0 215 #define R300_CMD_PACKET3_RAW 1 216 #define R300_CMD_PACKET0 1 217 #define R300_CMD_VPU 2 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 #define R300_CMD_PACKET3 3 220 #define R300_CMD_END3D 4 221 #define R300_CMD_CP_DELAY 5 222 #define R300_CMD_DMA_DISCARD 6 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 #define R300_CMD_WAIT 7 225 #define R300_WAIT_2D 0x1 226 #define R300_WAIT_3D 0x2 227 #define R300_WAIT_2D_CLEAN 0x3 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 #define R300_WAIT_3D_CLEAN 0x4 230 #define R300_NEW_WAIT_2D_3D 0x3 231 #define R300_NEW_WAIT_2D_2D_CLEAN 0x4 232 #define R300_NEW_WAIT_3D_3D_CLEAN 0x6 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 #define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8 235 #define R300_CMD_SCRATCH 8 236 #define R300_CMD_R500FP 9 237 typedef union { 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 unsigned int u; 240 struct { 241 unsigned char cmd_type, pad0, pad1, pad2; 242 } header; 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 struct { 245 unsigned char cmd_type, count, reglo, reghi; 246 } packet0; 247 struct { 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 unsigned char cmd_type, count, adrlo, adrhi; 250 } vpu; 251 struct { 252 unsigned char cmd_type, packet, pad0, pad1; 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 } packet3; 255 struct { 256 unsigned char cmd_type, packet; 257 unsigned short count; 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 } delay; 260 struct { 261 unsigned char cmd_type, buf_idx, pad0, pad1; 262 } dma; 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 struct { 265 unsigned char cmd_type, flags, pad0, pad1; 266 } wait; 267 struct { 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 unsigned char cmd_type, reg, n_bufs, flags; 270 } scratch; 271 struct { 272 unsigned char cmd_type, count, adrlo, adrhi_flags; 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 } r500fp; 275 } drm_r300_cmd_header_t; 276 #define RADEON_FRONT 0x1 277 #define RADEON_BACK 0x2 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 #define RADEON_DEPTH 0x4 280 #define RADEON_STENCIL 0x8 281 #define RADEON_CLEAR_FASTZ 0x80000000 282 #define RADEON_USE_HIERZ 0x40000000 283 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 284 #define RADEON_USE_COMP_ZBUF 0x20000000 285 #define R500FP_CONSTANT_TYPE (1 << 1) 286 #define R500FP_CONSTANT_CLAMP (1 << 2) 287 #define RADEON_POINTS 0x1 288 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 289 #define RADEON_LINES 0x2 290 #define RADEON_LINE_STRIP 0x3 291 #define RADEON_TRIANGLES 0x4 292 #define RADEON_TRIANGLE_FAN 0x5 293 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 294 #define RADEON_TRIANGLE_STRIP 0x6 295 #define RADEON_BUFFER_SIZE 65536 296 #define RADEON_INDEX_PRIM_OFFSET 20 297 #define RADEON_SCRATCH_REG_OFFSET 32 298 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 299 #define R600_SCRATCH_REG_OFFSET 256 300 #define RADEON_NR_SAREA_CLIPRECTS 12 301 #define RADEON_LOCAL_TEX_HEAP 0 302 #define RADEON_GART_TEX_HEAP 1 303 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 304 #define RADEON_NR_TEX_HEAPS 2 305 #define RADEON_NR_TEX_REGIONS 64 306 #define RADEON_LOG_TEX_GRANULARITY 16 307 #define RADEON_MAX_TEXTURE_LEVELS 12 308 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 309 #define RADEON_MAX_TEXTURE_UNITS 3 310 #define RADEON_MAX_SURFACES 8 311 #define RADEON_OFFSET_SHIFT 10 312 #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT) 313 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 314 #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1) 315 #endif 316 typedef struct { 317 unsigned int red; 318 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 319 unsigned int green; 320 unsigned int blue; 321 unsigned int alpha; 322 } radeon_color_regs_t; 323 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 324 typedef struct { 325 unsigned int pp_misc; 326 unsigned int pp_fog_color; 327 unsigned int re_solid_color; 328 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 329 unsigned int rb3d_blendcntl; 330 unsigned int rb3d_depthoffset; 331 unsigned int rb3d_depthpitch; 332 unsigned int rb3d_zstencilcntl; 333 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 334 unsigned int pp_cntl; 335 unsigned int rb3d_cntl; 336 unsigned int rb3d_coloroffset; 337 unsigned int re_width_height; 338 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 339 unsigned int rb3d_colorpitch; 340 unsigned int se_cntl; 341 unsigned int se_coord_fmt; 342 unsigned int re_line_pattern; 343 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 344 unsigned int re_line_state; 345 unsigned int se_line_width; 346 unsigned int pp_lum_matrix; 347 unsigned int pp_rot_matrix_0; 348 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 349 unsigned int pp_rot_matrix_1; 350 unsigned int rb3d_stencilrefmask; 351 unsigned int rb3d_ropcntl; 352 unsigned int rb3d_planemask; 353 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 354 unsigned int se_vport_xscale; 355 unsigned int se_vport_xoffset; 356 unsigned int se_vport_yscale; 357 unsigned int se_vport_yoffset; 358 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 359 unsigned int se_vport_zscale; 360 unsigned int se_vport_zoffset; 361 unsigned int se_cntl_status; 362 unsigned int re_top_left; 363 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 364 unsigned int re_misc; 365 } drm_radeon_context_regs_t; 366 typedef struct { 367 unsigned int se_zbias_factor; 368 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 369 unsigned int se_zbias_constant; 370 } drm_radeon_context2_regs_t; 371 typedef struct { 372 unsigned int pp_txfilter; 373 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 374 unsigned int pp_txformat; 375 unsigned int pp_txoffset; 376 unsigned int pp_txcblend; 377 unsigned int pp_txablend; 378 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 379 unsigned int pp_tfactor; 380 unsigned int pp_border_color; 381 } drm_radeon_texture_regs_t; 382 typedef struct { 383 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 384 unsigned int start; 385 unsigned int finish; 386 unsigned int prim : 8; 387 unsigned int stateidx : 8; 388 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 389 unsigned int numverts : 16; 390 unsigned int vc_format; 391 } drm_radeon_prim_t; 392 typedef struct { 393 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 394 drm_radeon_context_regs_t context; 395 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 396 drm_radeon_context2_regs_t context2; 397 unsigned int dirty; 398 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 399 } drm_radeon_state_t; 400 typedef struct { 401 drm_radeon_context_regs_t context_state; 402 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 403 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 404 unsigned int dirty; 405 unsigned int vertsize; 406 unsigned int vc_format; 407 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS]; 408 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 409 unsigned int nbox; 410 unsigned int last_frame; 411 unsigned int last_dispatch; 412 unsigned int last_clear; 413 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 414 struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 1]; 415 unsigned int tex_age[RADEON_NR_TEX_HEAPS]; 416 int ctx_owner; 417 int pfState; 418 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 419 int pfCurrentPage; 420 int crtc2_base; 421 int tiling_enabled; 422 } drm_radeon_sarea_t; 423 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 424 #define DRM_RADEON_CP_INIT 0x00 425 #define DRM_RADEON_CP_START 0x01 426 #define DRM_RADEON_CP_STOP 0x02 427 #define DRM_RADEON_CP_RESET 0x03 428 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 429 #define DRM_RADEON_CP_IDLE 0x04 430 #define DRM_RADEON_RESET 0x05 431 #define DRM_RADEON_FULLSCREEN 0x06 432 #define DRM_RADEON_SWAP 0x07 433 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 434 #define DRM_RADEON_CLEAR 0x08 435 #define DRM_RADEON_VERTEX 0x09 436 #define DRM_RADEON_INDICES 0x0A 437 #define DRM_RADEON_NOT_USED 438 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 439 #define DRM_RADEON_STIPPLE 0x0C 440 #define DRM_RADEON_INDIRECT 0x0D 441 #define DRM_RADEON_TEXTURE 0x0E 442 #define DRM_RADEON_VERTEX2 0x0F 443 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 444 #define DRM_RADEON_CMDBUF 0x10 445 #define DRM_RADEON_GETPARAM 0x11 446 #define DRM_RADEON_FLIP 0x12 447 #define DRM_RADEON_ALLOC 0x13 448 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 449 #define DRM_RADEON_FREE 0x14 450 #define DRM_RADEON_INIT_HEAP 0x15 451 #define DRM_RADEON_IRQ_EMIT 0x16 452 #define DRM_RADEON_IRQ_WAIT 0x17 453 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 454 #define DRM_RADEON_CP_RESUME 0x18 455 #define DRM_RADEON_SETPARAM 0x19 456 #define DRM_RADEON_SURF_ALLOC 0x1a 457 #define DRM_RADEON_SURF_FREE 0x1b 458 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 459 #define DRM_RADEON_GEM_INFO 0x1c 460 #define DRM_RADEON_GEM_CREATE 0x1d 461 #define DRM_RADEON_GEM_MMAP 0x1e 462 #define DRM_RADEON_GEM_PREAD 0x21 463 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 464 #define DRM_RADEON_GEM_PWRITE 0x22 465 #define DRM_RADEON_GEM_SET_DOMAIN 0x23 466 #define DRM_RADEON_GEM_WAIT_IDLE 0x24 467 #define DRM_RADEON_CS 0x26 468 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 469 #define DRM_RADEON_INFO 0x27 470 #define DRM_RADEON_GEM_SET_TILING 0x28 471 #define DRM_RADEON_GEM_GET_TILING 0x29 472 #define DRM_RADEON_GEM_BUSY 0x2a 473 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 474 #define DRM_RADEON_GEM_VA 0x2b 475 #define DRM_RADEON_GEM_OP 0x2c 476 #define DRM_RADEON_GEM_USERPTR 0x2d 477 #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) 478 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 479 #define DRM_IOCTL_RADEON_CP_START DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_START) 480 #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t) 481 #define DRM_IOCTL_RADEON_CP_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESET) 482 #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE) 483 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 484 #define DRM_IOCTL_RADEON_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_RESET) 485 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t) 486 #define DRM_IOCTL_RADEON_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_SWAP) 487 #define DRM_IOCTL_RADEON_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t) 488 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 489 #define DRM_IOCTL_RADEON_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t) 490 #define DRM_IOCTL_RADEON_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t) 491 #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t) 492 #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t) 493 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 494 #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t) 495 #define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t) 496 #define DRM_IOCTL_RADEON_CMDBUF DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t) 497 #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t) 498 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 499 #define DRM_IOCTL_RADEON_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_FLIP) 500 #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t) 501 #define DRM_IOCTL_RADEON_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t) 502 #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t) 503 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 504 #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t) 505 #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t) 506 #define DRM_IOCTL_RADEON_CP_RESUME DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME) 507 #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t) 508 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 509 #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t) 510 #define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t) 511 #define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info) 512 #define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create) 513 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 514 #define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap) 515 #define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread) 516 #define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite) 517 #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain) 518 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 519 #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle) 520 #define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs) 521 #define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info) 522 #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) 523 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 524 #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) 525 #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) 526 #define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va) 527 #define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op) 528 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 529 #define DRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr) 530 typedef struct drm_radeon_init { 531 enum { 532 RADEON_INIT_CP = 0x01, 533 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 534 RADEON_CLEANUP_CP = 0x02, 535 RADEON_INIT_R200_CP = 0x03, 536 RADEON_INIT_R300_CP = 0x04, 537 RADEON_INIT_R600_CP = 0x05 538 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 539 } func; 540 unsigned long sarea_priv_offset; 541 int is_pci; 542 int cp_mode; 543 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 544 int gart_size; 545 int ring_size; 546 int usec_timeout; 547 unsigned int fb_bpp; 548 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 549 unsigned int front_offset, front_pitch; 550 unsigned int back_offset, back_pitch; 551 unsigned int depth_bpp; 552 unsigned int depth_offset, depth_pitch; 553 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 554 unsigned long fb_offset; 555 unsigned long mmio_offset; 556 unsigned long ring_offset; 557 unsigned long ring_rptr_offset; 558 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 559 unsigned long buffers_offset; 560 unsigned long gart_textures_offset; 561 } drm_radeon_init_t; 562 typedef struct drm_radeon_cp_stop { 563 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 564 int flush; 565 int idle; 566 } drm_radeon_cp_stop_t; 567 typedef struct drm_radeon_fullscreen { 568 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 569 enum { 570 RADEON_INIT_FULLSCREEN = 0x01, 571 RADEON_CLEANUP_FULLSCREEN = 0x02 572 } func; 573 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 574 } drm_radeon_fullscreen_t; 575 #define CLEAR_X1 0 576 #define CLEAR_Y1 1 577 #define CLEAR_X2 2 578 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 579 #define CLEAR_Y2 3 580 #define CLEAR_DEPTH 4 581 typedef union drm_radeon_clear_rect { 582 float f[5]; 583 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 584 unsigned int ui[5]; 585 } drm_radeon_clear_rect_t; 586 typedef struct drm_radeon_clear { 587 unsigned int flags; 588 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 589 unsigned int clear_color; 590 unsigned int clear_depth; 591 unsigned int color_mask; 592 unsigned int depth_mask; 593 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 594 drm_radeon_clear_rect_t __user * depth_boxes; 595 } drm_radeon_clear_t; 596 typedef struct drm_radeon_vertex { 597 int prim; 598 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 599 int idx; 600 int count; 601 int discard; 602 } drm_radeon_vertex_t; 603 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 604 typedef struct drm_radeon_indices { 605 int prim; 606 int idx; 607 int start; 608 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 609 int end; 610 int discard; 611 } drm_radeon_indices_t; 612 typedef struct drm_radeon_vertex2 { 613 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 614 int idx; 615 int discard; 616 int nr_states; 617 drm_radeon_state_t __user * state; 618 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 619 int nr_prims; 620 drm_radeon_prim_t __user * prim; 621 } drm_radeon_vertex2_t; 622 typedef struct drm_radeon_cmd_buffer { 623 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 624 int bufsz; 625 char __user * buf; 626 int nbox; 627 struct drm_clip_rect __user * boxes; 628 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 629 } drm_radeon_cmd_buffer_t; 630 typedef struct drm_radeon_tex_image { 631 unsigned int x, y; 632 unsigned int width, height; 633 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 634 const void __user * data; 635 } drm_radeon_tex_image_t; 636 typedef struct drm_radeon_texture { 637 unsigned int offset; 638 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 639 int pitch; 640 int format; 641 int width; 642 int height; 643 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 644 drm_radeon_tex_image_t __user * image; 645 } drm_radeon_texture_t; 646 typedef struct drm_radeon_stipple { 647 unsigned int __user * mask; 648 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 649 } drm_radeon_stipple_t; 650 typedef struct drm_radeon_indirect { 651 int idx; 652 int start; 653 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 654 int end; 655 int discard; 656 } drm_radeon_indirect_t; 657 #define RADEON_CARD_PCI 0 658 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 659 #define RADEON_CARD_AGP 1 660 #define RADEON_CARD_PCIE 2 661 #define RADEON_PARAM_GART_BUFFER_OFFSET 1 662 #define RADEON_PARAM_LAST_FRAME 2 663 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 664 #define RADEON_PARAM_LAST_DISPATCH 3 665 #define RADEON_PARAM_LAST_CLEAR 4 666 #define RADEON_PARAM_IRQ_NR 5 667 #define RADEON_PARAM_GART_BASE 6 668 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 669 #define RADEON_PARAM_REGISTER_HANDLE 7 670 #define RADEON_PARAM_STATUS_HANDLE 8 671 #define RADEON_PARAM_SAREA_HANDLE 9 672 #define RADEON_PARAM_GART_TEX_HANDLE 10 673 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 674 #define RADEON_PARAM_SCRATCH_OFFSET 11 675 #define RADEON_PARAM_CARD_TYPE 12 676 #define RADEON_PARAM_VBLANK_CRTC 13 677 #define RADEON_PARAM_FB_LOCATION 14 678 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 679 #define RADEON_PARAM_NUM_GB_PIPES 15 680 #define RADEON_PARAM_DEVICE_ID 16 681 #define RADEON_PARAM_NUM_Z_PIPES 17 682 typedef struct drm_radeon_getparam { 683 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 684 int param; 685 void __user * value; 686 } drm_radeon_getparam_t; 687 #define RADEON_MEM_REGION_GART 1 688 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 689 #define RADEON_MEM_REGION_FB 2 690 typedef struct drm_radeon_mem_alloc { 691 int region; 692 int alignment; 693 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 694 int size; 695 int __user * region_offset; 696 } drm_radeon_mem_alloc_t; 697 typedef struct drm_radeon_mem_free { 698 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 699 int region; 700 int region_offset; 701 } drm_radeon_mem_free_t; 702 typedef struct drm_radeon_mem_init_heap { 703 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 704 int region; 705 int size; 706 int start; 707 } drm_radeon_mem_init_heap_t; 708 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 709 typedef struct drm_radeon_irq_emit { 710 int __user * irq_seq; 711 } drm_radeon_irq_emit_t; 712 typedef struct drm_radeon_irq_wait { 713 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 714 int irq_seq; 715 } drm_radeon_irq_wait_t; 716 typedef struct drm_radeon_setparam { 717 unsigned int param; 718 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 719 __s64 value; 720 } drm_radeon_setparam_t; 721 #define RADEON_SETPARAM_FB_LOCATION 1 722 #define RADEON_SETPARAM_SWITCH_TILING 2 723 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 724 #define RADEON_SETPARAM_PCIGART_LOCATION 3 725 #define RADEON_SETPARAM_NEW_MEMMAP 4 726 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 727 #define RADEON_SETPARAM_VBLANK_CRTC 6 728 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 729 typedef struct drm_radeon_surface_alloc { 730 unsigned int address; 731 unsigned int size; 732 unsigned int flags; 733 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 734 } drm_radeon_surface_alloc_t; 735 typedef struct drm_radeon_surface_free { 736 unsigned int address; 737 } drm_radeon_surface_free_t; 738 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 739 #define DRM_RADEON_VBLANK_CRTC1 1 740 #define DRM_RADEON_VBLANK_CRTC2 2 741 #define RADEON_GEM_DOMAIN_CPU 0x1 742 #define RADEON_GEM_DOMAIN_GTT 0x2 743 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 744 #define RADEON_GEM_DOMAIN_VRAM 0x4 745 struct drm_radeon_gem_info { 746 uint64_t gart_size; 747 uint64_t vram_size; 748 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 749 uint64_t vram_visible; 750 }; 751 #define RADEON_GEM_NO_BACKING_STORE (1 << 0) 752 #define RADEON_GEM_GTT_UC (1 << 1) 753 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 754 #define RADEON_GEM_GTT_WC (1 << 2) 755 #define RADEON_GEM_CPU_ACCESS (1 << 3) 756 #define RADEON_GEM_NO_CPU_ACCESS (1 << 4) 757 struct drm_radeon_gem_create { 758 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 759 uint64_t size; 760 uint64_t alignment; 761 uint32_t handle; 762 uint32_t initial_domain; 763 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 764 uint32_t flags; 765 }; 766 #define RADEON_GEM_USERPTR_READONLY (1 << 0) 767 #define RADEON_GEM_USERPTR_ANONONLY (1 << 1) 768 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 769 #define RADEON_GEM_USERPTR_VALIDATE (1 << 2) 770 #define RADEON_GEM_USERPTR_REGISTER (1 << 3) 771 struct drm_radeon_gem_userptr { 772 uint64_t addr; 773 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 774 uint64_t size; 775 uint32_t flags; 776 uint32_t handle; 777 }; 778 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 779 #define RADEON_TILING_MACRO 0x1 780 #define RADEON_TILING_MICRO 0x2 781 #define RADEON_TILING_SWAP_16BIT 0x4 782 #define RADEON_TILING_SWAP_32BIT 0x8 783 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 784 #define RADEON_TILING_SURFACE 0x10 785 #define RADEON_TILING_MICRO_SQUARE 0x20 786 #define RADEON_TILING_EG_BANKW_SHIFT 8 787 #define RADEON_TILING_EG_BANKW_MASK 0xf 788 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 789 #define RADEON_TILING_EG_BANKH_SHIFT 12 790 #define RADEON_TILING_EG_BANKH_MASK 0xf 791 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 792 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf 793 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 794 #define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24 795 #define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf 796 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 797 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf 798 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 799 struct drm_radeon_gem_set_tiling { 800 uint32_t handle; 801 uint32_t tiling_flags; 802 uint32_t pitch; 803 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 804 }; 805 struct drm_radeon_gem_get_tiling { 806 uint32_t handle; 807 uint32_t tiling_flags; 808 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 809 uint32_t pitch; 810 }; 811 struct drm_radeon_gem_mmap { 812 uint32_t handle; 813 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 814 uint32_t pad; 815 uint64_t offset; 816 uint64_t size; 817 uint64_t addr_ptr; 818 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 819 }; 820 struct drm_radeon_gem_set_domain { 821 uint32_t handle; 822 uint32_t read_domains; 823 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 824 uint32_t write_domain; 825 }; 826 struct drm_radeon_gem_wait_idle { 827 uint32_t handle; 828 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 829 uint32_t pad; 830 }; 831 struct drm_radeon_gem_busy { 832 uint32_t handle; 833 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 834 uint32_t domain; 835 }; 836 struct drm_radeon_gem_pread { 837 uint32_t handle; 838 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 839 uint32_t pad; 840 uint64_t offset; 841 uint64_t size; 842 uint64_t data_ptr; 843 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 844 }; 845 struct drm_radeon_gem_pwrite { 846 uint32_t handle; 847 uint32_t pad; 848 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 849 uint64_t offset; 850 uint64_t size; 851 uint64_t data_ptr; 852 }; 853 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 854 struct drm_radeon_gem_op { 855 uint32_t handle; 856 uint32_t op; 857 uint64_t value; 858 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 859 }; 860 #define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0 861 #define RADEON_GEM_OP_SET_INITIAL_DOMAIN 1 862 #define RADEON_VA_MAP 1 863 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 864 #define RADEON_VA_UNMAP 2 865 #define RADEON_VA_RESULT_OK 0 866 #define RADEON_VA_RESULT_ERROR 1 867 #define RADEON_VA_RESULT_VA_EXIST 2 868 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 869 #define RADEON_VM_PAGE_VALID (1 << 0) 870 #define RADEON_VM_PAGE_READABLE (1 << 1) 871 #define RADEON_VM_PAGE_WRITEABLE (1 << 2) 872 #define RADEON_VM_PAGE_SYSTEM (1 << 3) 873 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 874 #define RADEON_VM_PAGE_SNOOPED (1 << 4) 875 struct drm_radeon_gem_va { 876 uint32_t handle; 877 uint32_t operation; 878 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 879 uint32_t vm_id; 880 uint32_t flags; 881 uint64_t offset; 882 }; 883 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 884 #define RADEON_CHUNK_ID_RELOCS 0x01 885 #define RADEON_CHUNK_ID_IB 0x02 886 #define RADEON_CHUNK_ID_FLAGS 0x03 887 #define RADEON_CHUNK_ID_CONST_IB 0x04 888 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 889 #define RADEON_CS_KEEP_TILING_FLAGS 0x01 890 #define RADEON_CS_USE_VM 0x02 891 #define RADEON_CS_END_OF_FRAME 0x04 892 #define RADEON_CS_RING_GFX 0 893 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 894 #define RADEON_CS_RING_COMPUTE 1 895 #define RADEON_CS_RING_DMA 2 896 #define RADEON_CS_RING_UVD 3 897 #define RADEON_CS_RING_VCE 4 898 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 899 struct drm_radeon_cs_chunk { 900 uint32_t chunk_id; 901 uint32_t length_dw; 902 uint64_t chunk_data; 903 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 904 }; 905 #define RADEON_RELOC_PRIO_MASK (0xf << 0) 906 struct drm_radeon_cs_reloc { 907 uint32_t handle; 908 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 909 uint32_t read_domains; 910 uint32_t write_domain; 911 uint32_t flags; 912 }; 913 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 914 struct drm_radeon_cs { 915 uint32_t num_chunks; 916 uint32_t cs_id; 917 uint64_t chunks; 918 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 919 uint64_t gart_limit; 920 uint64_t vram_limit; 921 }; 922 #define RADEON_INFO_DEVICE_ID 0x00 923 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 924 #define RADEON_INFO_NUM_GB_PIPES 0x01 925 #define RADEON_INFO_NUM_Z_PIPES 0x02 926 #define RADEON_INFO_ACCEL_WORKING 0x03 927 #define RADEON_INFO_CRTC_FROM_ID 0x04 928 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 929 #define RADEON_INFO_ACCEL_WORKING2 0x05 930 #define RADEON_INFO_TILING_CONFIG 0x06 931 #define RADEON_INFO_WANT_HYPERZ 0x07 932 #define RADEON_INFO_WANT_CMASK 0x08 933 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 934 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 935 #define RADEON_INFO_NUM_BACKENDS 0x0a 936 #define RADEON_INFO_NUM_TILE_PIPES 0x0b 937 #define RADEON_INFO_FUSION_GART_WORKING 0x0c 938 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 939 #define RADEON_INFO_BACKEND_MAP 0x0d 940 #define RADEON_INFO_VA_START 0x0e 941 #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f 942 #define RADEON_INFO_MAX_PIPES 0x10 943 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 944 #define RADEON_INFO_TIMESTAMP 0x11 945 #define RADEON_INFO_MAX_SE 0x12 946 #define RADEON_INFO_MAX_SH_PER_SE 0x13 947 #define RADEON_INFO_FASTFB_WORKING 0x14 948 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 949 #define RADEON_INFO_RING_WORKING 0x15 950 #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16 951 #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17 952 #define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18 953 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 954 #define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19 955 #define RADEON_INFO_MAX_SCLK 0x1a 956 #define RADEON_INFO_VCE_FW_VERSION 0x1b 957 #define RADEON_INFO_VCE_FB_VERSION 0x1c 958 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 959 #define RADEON_INFO_NUM_BYTES_MOVED 0x1d 960 #define RADEON_INFO_VRAM_USAGE 0x1e 961 #define RADEON_INFO_GTT_USAGE 0x1f 962 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20 963 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 964 #define RADEON_INFO_CURRENT_GPU_TEMP 0x21 965 #define RADEON_INFO_CURRENT_GPU_SCLK 0x22 966 #define RADEON_INFO_CURRENT_GPU_MCLK 0x23 967 #define RADEON_INFO_READ_REG 0x24 968 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 969 #define RADEON_INFO_VA_UNMAP_WORKING 0x25 970 #define RADEON_INFO_GPU_RESET_COUNTER 0x26 971 struct drm_radeon_info { 972 uint32_t request; 973 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 974 uint32_t pad; 975 uint64_t value; 976 }; 977 #define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8 978 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 979 #define SI_TILE_MODE_COLOR_1D 13 980 #define SI_TILE_MODE_COLOR_1D_SCANOUT 9 981 #define SI_TILE_MODE_COLOR_2D_8BPP 14 982 #define SI_TILE_MODE_COLOR_2D_16BPP 15 983 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 984 #define SI_TILE_MODE_COLOR_2D_32BPP 16 985 #define SI_TILE_MODE_COLOR_2D_64BPP 17 986 #define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11 987 #define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12 988 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 989 #define SI_TILE_MODE_DEPTH_STENCIL_1D 4 990 #define SI_TILE_MODE_DEPTH_STENCIL_2D 0 991 #define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3 992 #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3 993 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 994 #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2 995 #define CIK_TILE_MODE_DEPTH_STENCIL_1D 5 996 #endif 997
