1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _ASM_DMA_H 20 #define _ASM_DMA_H 21 #include <linux/spinlock.h> 22 #include <asm/io.h> 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 #include <linux/delay.h> 25 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER 26 #define dma_outb outb_p 27 #else 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 #define dma_outb outb 30 #endif 31 #define dma_inb inb 32 #define MAX_DMA_CHANNELS 8 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 #define MAX_DMA_ADDRESS (PAGE_OFFSET+0x1000000) 35 #define IO_DMA1_BASE 0x00 36 #define IO_DMA2_BASE 0xC0 37 #define DMA1_CMD_REG 0x08 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 #define DMA1_STAT_REG 0x08 40 #define DMA1_REQ_REG 0x09 41 #define DMA1_MASK_REG 0x0A 42 #define DMA1_MODE_REG 0x0B 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 #define DMA1_CLEAR_FF_REG 0x0C 45 #define DMA1_TEMP_REG 0x0D 46 #define DMA1_RESET_REG 0x0D 47 #define DMA1_CLR_MASK_REG 0x0E 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 #define DMA1_MASK_ALL_REG 0x0F 50 #define DMA2_CMD_REG 0xD0 51 #define DMA2_STAT_REG 0xD0 52 #define DMA2_REQ_REG 0xD2 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 #define DMA2_MASK_REG 0xD4 55 #define DMA2_MODE_REG 0xD6 56 #define DMA2_CLEAR_FF_REG 0xD8 57 #define DMA2_TEMP_REG 0xDA 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 #define DMA2_RESET_REG 0xDA 60 #define DMA2_CLR_MASK_REG 0xDC 61 #define DMA2_MASK_ALL_REG 0xDE 62 #define DMA_ADDR_0 0x00 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 #define DMA_ADDR_1 0x02 65 #define DMA_ADDR_2 0x04 66 #define DMA_ADDR_3 0x06 67 #define DMA_ADDR_4 0xC0 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 #define DMA_ADDR_5 0xC4 70 #define DMA_ADDR_6 0xC8 71 #define DMA_ADDR_7 0xCC 72 #define DMA_CNT_0 0x01 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 #define DMA_CNT_1 0x03 75 #define DMA_CNT_2 0x05 76 #define DMA_CNT_3 0x07 77 #define DMA_CNT_4 0xC2 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 #define DMA_CNT_5 0xC6 80 #define DMA_CNT_6 0xCA 81 #define DMA_CNT_7 0xCE 82 #define DMA_PAGE_0 0x87 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 #define DMA_PAGE_1 0x83 85 #define DMA_PAGE_2 0x81 86 #define DMA_PAGE_3 0x82 87 #define DMA_PAGE_5 0x8B 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 #define DMA_PAGE_6 0x89 90 #define DMA_PAGE_7 0x8A 91 #define DMA_MODE_READ 0x44 92 #define DMA_MODE_WRITE 0x48 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 #define DMA_MODE_CASCADE 0xC0 95 #define DMA_AUTOINIT 0x10 96 #define isa_dma_bridge_buggy (0) 97 #endif 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99
