1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the target-independent interfaces used by SelectionDAG 11 // instruction selection generators. 12 // 13 //===----------------------------------------------------------------------===// 14 15 //===----------------------------------------------------------------------===// 16 // Selection DAG Type Constraint definitions. 17 // 18 // Note that the semantics of these constraints are hard coded into tblgen. To 19 // modify or add constraints, you have to hack tblgen. 20 // 21 22 class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24 } 25 26 // SDTCisVT - The specified operand has exactly this VT. 27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29 } 30 31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33 // SDTCisInt - The specified operand has integer type. 34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36 // SDTCisFP - The specified operand has floating-point type. 37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39 // SDTCisVec - The specified operand has a vector type. 40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 41 42 // SDTCisSameAs - The two specified operands have identical types. 43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 44 int OtherOperandNum = OtherOp; 45 } 46 47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 48 // smaller than the 'Other' operand. 49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 50 int OtherOperandNum = OtherOp; 51 } 52 53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 54 int BigOperandNum = BigOp; 55 } 56 57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 58 /// type as the element type of OtherOp, which is a vector type. 59 class SDTCisEltOfVec<int ThisOp, int OtherOp> 60 : SDTypeConstraint<ThisOp> { 61 int OtherOpNum = OtherOp; 62 } 63 64 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type 65 /// with length less that of OtherOp, which is a vector type. 66 class SDTCisSubVecOfVec<int ThisOp, int OtherOp> 67 : SDTypeConstraint<ThisOp> { 68 int OtherOpNum = OtherOp; 69 } 70 71 // SDTCVecEltisVT - The specified operand is vector type with element type 72 // of VT. 73 class SDTCVecEltisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 74 ValueType VT = vt; 75 } 76 77 // SDTCisSameNumEltsAs - The two specified operands have identical number 78 // of elements. 79 class SDTCisSameNumEltsAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 80 int OtherOperandNum = OtherOp; 81 } 82 83 // SDTCisSameSizeAs - The two specified operands have identical size. 84 class SDTCisSameSizeAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 85 int OtherOperandNum = OtherOp; 86 } 87 88 //===----------------------------------------------------------------------===// 89 // Selection DAG Type Profile definitions. 90 // 91 // These use the constraints defined above to describe the type requirements of 92 // the various nodes. These are not hard coded into tblgen, allowing targets to 93 // add their own if needed. 94 // 95 96 // SDTypeProfile - This profile describes the type requirements of a Selection 97 // DAG node. 98 class SDTypeProfile<int numresults, int numoperands, 99 list<SDTypeConstraint> constraints> { 100 int NumResults = numresults; 101 int NumOperands = numoperands; 102 list<SDTypeConstraint> Constraints = constraints; 103 } 104 105 // Builtin profiles. 106 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 107 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 108 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 109 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 110 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 111 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 112 113 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 114 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 115 ]>; 116 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 117 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 118 ]>; 119 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem 120 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0> 121 ]>; 122 123 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 124 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 125 ]>; 126 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 127 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 128 ]>; 129 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 130 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 131 ]>; 132 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz 133 SDTCisSameAs<0, 1>, SDTCisInt<0> 134 ]>; 135 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 136 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 137 ]>; 138 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 139 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1> 140 ]>; 141 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 142 SDTCisSameAs<0, 1>, SDTCisFP<0> 143 ]>; 144 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 145 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> 146 ]>; 147 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 148 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> 149 ]>; 150 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 151 SDTCisFP<0>, SDTCisInt<1> 152 ]>; 153 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 154 SDTCisInt<0>, SDTCisFP<1> 155 ]>; 156 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 157 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 158 SDTCisVTSmallerThanOp<2, 1> 159 ]>; 160 161 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 162 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 163 ]>; 164 165 def SDTSelect : SDTypeProfile<1, 3, [ // select 166 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 167 ]>; 168 169 def SDTVSelect : SDTypeProfile<1, 3, [ // vselect 170 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 171 ]>; 172 173 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 174 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 175 SDTCisVT<5, OtherVT> 176 ]>; 177 178 def SDTBr : SDTypeProfile<0, 1, [ // br 179 SDTCisVT<0, OtherVT> 180 ]>; 181 182 def SDTBrCC : SDTypeProfile<0, 4, [ // brcc 183 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 184 ]>; 185 186 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 187 SDTCisInt<0>, SDTCisVT<1, OtherVT> 188 ]>; 189 190 def SDTBrind : SDTypeProfile<0, 1, [ // brind 191 SDTCisPtrTy<0> 192 ]>; 193 194 def SDTCatchret : SDTypeProfile<0, 2, [ // catchret 195 SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT> 196 ]>; 197 198 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 199 200 def SDTLoad : SDTypeProfile<1, 1, [ // load 201 SDTCisPtrTy<1> 202 ]>; 203 204 def SDTStore : SDTypeProfile<0, 2, [ // store 205 SDTCisPtrTy<1> 206 ]>; 207 208 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 209 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 210 ]>; 211 212 def SDTMaskedStore: SDTypeProfile<0, 3, [ // masked store 213 SDTCisPtrTy<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameNumEltsAs<1, 2> 214 ]>; 215 216 def SDTMaskedLoad: SDTypeProfile<1, 3, [ // masked load 217 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>, 218 SDTCisSameNumEltsAs<0, 2> 219 ]>; 220 221 def SDTMaskedGather: SDTypeProfile<2, 3, [ // masked gather 222 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>, 223 SDTCisPtrTy<4>, SDTCVecEltisVT<1, i1>, SDTCisSameNumEltsAs<0, 1> 224 ]>; 225 226 def SDTMaskedScatter: SDTypeProfile<1, 3, [ // masked scatter 227 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameNumEltsAs<0, 1>, 228 SDTCVecEltisVT<0, i1>, SDTCisPtrTy<3> 229 ]>; 230 231 def SDTVecShuffle : SDTypeProfile<1, 2, [ 232 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 233 ]>; 234 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 235 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 236 ]>; 237 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 238 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 239 ]>; 240 241 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract 242 SDTCisSubVecOfVec<0,1>, SDTCisInt<2> 243 ]>; 244 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert 245 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3> 246 ]>; 247 248 def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch 249 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1> 250 ]>; 251 252 def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barrier 253 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 254 SDTCisInt<0> 255 ]>; 256 def SDTAtomicFence : SDTypeProfile<0, 2, [ 257 SDTCisSameAs<0,1>, SDTCisPtrTy<0> 258 ]>; 259 def SDTAtomic3 : SDTypeProfile<1, 3, [ 260 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 261 ]>; 262 def SDTAtomic2 : SDTypeProfile<1, 2, [ 263 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 264 ]>; 265 def SDTAtomicStore : SDTypeProfile<0, 2, [ 266 SDTCisPtrTy<0>, SDTCisInt<1> 267 ]>; 268 def SDTAtomicLoad : SDTypeProfile<1, 1, [ 269 SDTCisInt<0>, SDTCisPtrTy<1> 270 ]>; 271 272 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 273 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 274 ]>; 275 276 class SDCallSeqStart<list<SDTypeConstraint> constraints> : 277 SDTypeProfile<0, 1, constraints>; 278 class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 279 SDTypeProfile<0, 2, constraints>; 280 281 //===----------------------------------------------------------------------===// 282 // Selection DAG Node Properties. 283 // 284 // Note: These are hard coded into tblgen. 285 // 286 class SDNodeProperty; 287 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 288 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 289 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 290 def SDNPOutGlue : SDNodeProperty; // Write a flag result 291 def SDNPInGlue : SDNodeProperty; // Read a flag operand 292 def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand 293 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 294 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 295 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 296 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 297 def SDNPVariadic : SDNodeProperty; // Node has variable arguments. 298 def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match 299 def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent 300 301 //===----------------------------------------------------------------------===// 302 // Selection DAG Pattern Operations 303 class SDPatternOperator; 304 305 //===----------------------------------------------------------------------===// 306 // Selection DAG Node definitions. 307 // 308 class SDNode<string opcode, SDTypeProfile typeprof, 309 list<SDNodeProperty> props = [], string sdclass = "SDNode"> 310 : SDPatternOperator { 311 string Opcode = opcode; 312 string SDClass = sdclass; 313 list<SDNodeProperty> Properties = props; 314 SDTypeProfile TypeProfile = typeprof; 315 } 316 317 // Special TableGen-recognized dag nodes 318 def set; 319 def implicit; 320 def node; 321 def srcvalue; 322 323 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 324 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 325 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 326 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 327 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 328 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 329 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 330 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 331 "GlobalAddressSDNode">; 332 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 333 "GlobalAddressSDNode">; 334 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 335 "GlobalAddressSDNode">; 336 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 337 "GlobalAddressSDNode">; 338 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 339 "ConstantPoolSDNode">; 340 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 341 "ConstantPoolSDNode">; 342 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 343 "JumpTableSDNode">; 344 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 345 "JumpTableSDNode">; 346 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 347 "FrameIndexSDNode">; 348 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 349 "FrameIndexSDNode">; 350 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 351 "ExternalSymbolSDNode">; 352 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 353 "ExternalSymbolSDNode">; 354 def mcsym: SDNode<"ISD::MCSymbol", SDTPtrLeaf, [], "MCSymbolSDNode">; 355 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 356 "BlockAddressSDNode">; 357 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 358 "BlockAddressSDNode">; 359 360 def add : SDNode<"ISD::ADD" , SDTIntBinOp , 361 [SDNPCommutative, SDNPAssociative]>; 362 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 363 def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 364 [SDNPCommutative, SDNPAssociative]>; 365 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 366 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 367 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 368 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 369 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 370 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 371 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 372 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 373 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>; 374 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>; 375 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 376 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 377 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 378 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 379 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 380 def and : SDNode<"ISD::AND" , SDTIntBinOp, 381 [SDNPCommutative, SDNPAssociative]>; 382 def or : SDNode<"ISD::OR" , SDTIntBinOp, 383 [SDNPCommutative, SDNPAssociative]>; 384 def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 385 [SDNPCommutative, SDNPAssociative]>; 386 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 387 [SDNPCommutative, SDNPOutGlue]>; 388 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 389 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>; 390 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 391 [SDNPOutGlue]>; 392 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 393 [SDNPOutGlue, SDNPInGlue]>; 394 def smin : SDNode<"ISD::SMIN" , SDTIntBinOp>; 395 def smax : SDNode<"ISD::SMAX" , SDTIntBinOp>; 396 def umin : SDNode<"ISD::UMIN" , SDTIntBinOp>; 397 def umax : SDNode<"ISD::UMAX" , SDTIntBinOp>; 398 399 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 400 def bitreverse : SDNode<"ISD::BITREVERSE" , SDTIntUnaryOp>; 401 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 402 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 403 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 404 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 405 def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>; 406 def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>; 407 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 408 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 409 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 410 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 411 def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>; 412 def addrspacecast : SDNode<"ISD::ADDRSPACECAST", SDTUnaryOp>; 413 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 414 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 415 416 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 417 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 418 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 419 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 420 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 421 def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>; 422 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>; 423 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 424 def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp>; 425 def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp>; 426 def fminnan : SDNode<"ISD::FMINNAN" , SDTFPBinOp>; 427 def fmaxnan : SDNode<"ISD::FMAXNAN" , SDTFPBinOp>; 428 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; 429 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 430 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 431 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 432 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 433 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 434 def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>; 435 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 436 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 437 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 438 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 439 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 440 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 441 def frnd : SDNode<"ISD::FROUND" , SDTFPUnaryOp>; 442 443 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 444 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 445 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 446 447 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 448 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 449 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 450 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 451 def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>; 452 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>; 453 454 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 455 def select : SDNode<"ISD::SELECT" , SDTSelect>; 456 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>; 457 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 458 459 def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>; 460 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 461 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 462 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 463 def catchret : SDNode<"ISD::CATCHRET" , SDTCatchret, 464 [SDNPHasChain, SDNPSideEffect]>; 465 def cleanupret : SDNode<"ISD::CLEANUPRET" , SDTNone, [SDNPHasChain]>; 466 def catchpad : SDNode<"ISD::CATCHPAD" , SDTNone, 467 [SDNPHasChain, SDNPSideEffect]>; 468 469 def trap : SDNode<"ISD::TRAP" , SDTNone, 470 [SDNPHasChain, SDNPSideEffect]>; 471 def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone, 472 [SDNPHasChain, SDNPSideEffect]>; 473 474 def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, 475 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 476 SDNPMemOperand]>; 477 478 def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf, 479 [SDNPHasChain, SDNPSideEffect]>; 480 481 def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence, 482 [SDNPHasChain, SDNPSideEffect]>; 483 484 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, 485 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 486 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, 487 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 488 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, 489 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 490 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, 491 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 492 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, 493 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 494 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, 495 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 496 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, 497 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 498 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, 499 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 500 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, 501 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 502 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, 503 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 504 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, 505 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 506 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, 507 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 508 def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad, 509 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 510 def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore, 511 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 512 513 def masked_store : SDNode<"ISD::MSTORE", SDTMaskedStore, 514 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 515 def masked_load : SDNode<"ISD::MLOAD", SDTMaskedLoad, 516 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 517 def masked_scatter : SDNode<"ISD::MSCATTER", SDTMaskedScatter, 518 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 519 def masked_gather : SDNode<"ISD::MGATHER", SDTMaskedGather, 520 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 521 522 // Do not use ld, st directly. Use load, extload, sextload, zextload, store, 523 // and truncst (see below). 524 def ld : SDNode<"ISD::LOAD" , SDTLoad, 525 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 526 def st : SDNode<"ISD::STORE" , SDTStore, 527 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 528 def ist : SDNode<"ISD::STORE" , SDTIStore, 529 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 530 531 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 532 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 533 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 534 []>; 535 536 // vector_extract/vector_insert are deprecated. extractelt/insertelt 537 // are preferred. 538 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 539 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 540 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 541 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 542 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS", 543 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>; 544 545 // This operator does not do subvector type checking. The ARM 546 // backend, at least, needs it. 547 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR", 548 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>, 549 []>; 550 551 // This operator does subvector type checking. 552 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>; 553 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>; 554 555 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 556 // these internally. Don't reference these directly. 557 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 558 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 559 [SDNPHasChain]>; 560 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 561 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 562 [SDNPHasChain]>; 563 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 564 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 565 566 // Do not use cvt directly. Use cvt forms below 567 def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>; 568 569 def SDT_assertext : SDTypeProfile<1, 1, 570 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>; 571 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>; 572 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>; 573 574 575 //===----------------------------------------------------------------------===// 576 // Selection DAG Condition Codes 577 578 class CondCode; // ISD::CondCode enums 579 def SETOEQ : CondCode; def SETOGT : CondCode; 580 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 581 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 582 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 583 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 584 585 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 586 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 587 588 589 //===----------------------------------------------------------------------===// 590 // Selection DAG Node Transformation Functions. 591 // 592 // This mechanism allows targets to manipulate nodes in the output DAG once a 593 // match has been formed. This is typically used to manipulate immediate 594 // values. 595 // 596 class SDNodeXForm<SDNode opc, code xformFunction> { 597 SDNode Opcode = opc; 598 code XFormFunction = xformFunction; 599 } 600 601 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 602 603 //===----------------------------------------------------------------------===// 604 // PatPred Subclasses. 605 // 606 // These allow specifying different sorts of predicates that control whether a 607 // node is matched. 608 // 609 class PatPred; 610 611 class CodePatPred<code predicate> : PatPred { 612 code PredicateCode = predicate; 613 } 614 615 616 //===----------------------------------------------------------------------===// 617 // Selection DAG Pattern Fragments. 618 // 619 // Pattern fragments are reusable chunks of dags that match specific things. 620 // They can take arguments and have C++ predicates that control whether they 621 // match. They are intended to make the patterns for common instructions more 622 // compact and readable. 623 // 624 625 /// PatFrag - Represents a pattern fragment. This can match something on the 626 /// DAG, from a single node to multiple nested other fragments. 627 /// 628 class PatFrag<dag ops, dag frag, code pred = [{}], 629 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator { 630 dag Operands = ops; 631 dag Fragment = frag; 632 code PredicateCode = pred; 633 code ImmediateCode = [{}]; 634 SDNodeXForm OperandTransform = xform; 635 } 636 637 // OutPatFrag is a pattern fragment that is used as part of an output pattern 638 // (not an input pattern). These do not have predicates or transforms, but are 639 // used to avoid repeated subexpressions in output patterns. 640 class OutPatFrag<dag ops, dag frag> 641 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>; 642 643 // PatLeaf's are pattern fragments that have no operands. This is just a helper 644 // to define immediates and other common things concisely. 645 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 646 : PatFrag<(ops), frag, pred, xform>; 647 648 649 // ImmLeaf is a pattern fragment with a constraint on the immediate. The 650 // constraint is a function that is run on the immediate (always with the value 651 // sign extended out to an int64_t) as Imm. For example: 652 // 653 // def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>; 654 // 655 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also 656 // is preferred over using PatLeaf because it allows the code generator to 657 // reason more about the constraint. 658 // 659 // If FastIsel should ignore all instructions that have an operand of this type, 660 // the FastIselShouldIgnore flag can be set. This is an optimization to reduce 661 // the code size of the generated fast instruction selector. 662 class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 663 : PatFrag<(ops), (vt imm), [{}], xform> { 664 let ImmediateCode = pred; 665 bit FastIselShouldIgnore = 0; 666 } 667 668 669 // Leaf fragments. 670 671 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 672 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 673 674 def immAllOnesV: PatLeaf<(build_vector), [{ 675 return ISD::isBuildVectorAllOnes(N); 676 }]>; 677 def immAllZerosV: PatLeaf<(build_vector), [{ 678 return ISD::isBuildVectorAllZeros(N); 679 }]>; 680 681 682 683 // Other helper fragments. 684 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 685 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 686 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 687 688 // null_frag - The null pattern operator is used in multiclass instantiations 689 // which accept an SDPatternOperator for use in matching patterns for internal 690 // definitions. When expanding a pattern, if the null fragment is referenced 691 // in the expansion, the pattern is discarded and it is as-if '[]' had been 692 // specified. This allows multiclasses to have the isel patterns be optional. 693 def null_frag : SDPatternOperator; 694 695 // load fragments. 696 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ 697 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 698 }]>; 699 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 700 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 701 }]>; 702 703 // extending load fragments. 704 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 705 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 706 }]>; 707 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 708 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 709 }]>; 710 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 711 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 712 }]>; 713 714 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 715 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 716 }]>; 717 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 718 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 719 }]>; 720 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 721 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 722 }]>; 723 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 724 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 725 }]>; 726 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 727 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32; 728 }]>; 729 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 730 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64; 731 }]>; 732 733 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 734 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 735 }]>; 736 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 737 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 738 }]>; 739 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 740 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 741 }]>; 742 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 743 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 744 }]>; 745 746 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 747 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 748 }]>; 749 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 750 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 751 }]>; 752 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 753 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 754 }]>; 755 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 756 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 757 }]>; 758 759 def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 760 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1; 761 }]>; 762 def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 763 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 764 }]>; 765 def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 766 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 767 }]>; 768 def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 769 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 770 }]>; 771 def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 772 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f32; 773 }]>; 774 def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 775 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f64; 776 }]>; 777 778 def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 779 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1; 780 }]>; 781 def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 782 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 783 }]>; 784 def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 785 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 786 }]>; 787 def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 788 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 789 }]>; 790 791 def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 792 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1; 793 }]>; 794 def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 795 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 796 }]>; 797 def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 798 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 799 }]>; 800 def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 801 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 802 }]>; 803 804 // store fragments. 805 def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 806 (st node:$val, node:$ptr), [{ 807 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 808 }]>; 809 def store : PatFrag<(ops node:$val, node:$ptr), 810 (unindexedstore node:$val, node:$ptr), [{ 811 return !cast<StoreSDNode>(N)->isTruncatingStore(); 812 }]>; 813 814 // truncstore fragments. 815 def truncstore : PatFrag<(ops node:$val, node:$ptr), 816 (unindexedstore node:$val, node:$ptr), [{ 817 return cast<StoreSDNode>(N)->isTruncatingStore(); 818 }]>; 819 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 820 (truncstore node:$val, node:$ptr), [{ 821 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 822 }]>; 823 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 824 (truncstore node:$val, node:$ptr), [{ 825 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 826 }]>; 827 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 828 (truncstore node:$val, node:$ptr), [{ 829 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 830 }]>; 831 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 832 (truncstore node:$val, node:$ptr), [{ 833 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 834 }]>; 835 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 836 (truncstore node:$val, node:$ptr), [{ 837 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64; 838 }]>; 839 840 def truncstorevi8 : PatFrag<(ops node:$val, node:$ptr), 841 (truncstore node:$val, node:$ptr), [{ 842 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8; 843 }]>; 844 845 def truncstorevi16 : PatFrag<(ops node:$val, node:$ptr), 846 (truncstore node:$val, node:$ptr), [{ 847 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16; 848 }]>; 849 850 def truncstorevi32 : PatFrag<(ops node:$val, node:$ptr), 851 (truncstore node:$val, node:$ptr), [{ 852 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32; 853 }]>; 854 855 // indexed store fragments. 856 def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 857 (ist node:$val, node:$base, node:$offset), [{ 858 return !cast<StoreSDNode>(N)->isTruncatingStore(); 859 }]>; 860 861 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 862 (istore node:$val, node:$base, node:$offset), [{ 863 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 864 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 865 }]>; 866 867 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 868 (ist node:$val, node:$base, node:$offset), [{ 869 return cast<StoreSDNode>(N)->isTruncatingStore(); 870 }]>; 871 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 872 (itruncstore node:$val, node:$base, node:$offset), [{ 873 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 874 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 875 }]>; 876 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 877 (pre_truncst node:$val, node:$base, node:$offset), [{ 878 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 879 }]>; 880 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 881 (pre_truncst node:$val, node:$base, node:$offset), [{ 882 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 883 }]>; 884 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 885 (pre_truncst node:$val, node:$base, node:$offset), [{ 886 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 887 }]>; 888 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 889 (pre_truncst node:$val, node:$base, node:$offset), [{ 890 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 891 }]>; 892 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 893 (pre_truncst node:$val, node:$base, node:$offset), [{ 894 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 895 }]>; 896 897 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 898 (istore node:$val, node:$ptr, node:$offset), [{ 899 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 900 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 901 }]>; 902 903 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 904 (itruncstore node:$val, node:$base, node:$offset), [{ 905 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 906 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 907 }]>; 908 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 909 (post_truncst node:$val, node:$base, node:$offset), [{ 910 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 911 }]>; 912 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 913 (post_truncst node:$val, node:$base, node:$offset), [{ 914 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 915 }]>; 916 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 917 (post_truncst node:$val, node:$base, node:$offset), [{ 918 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 919 }]>; 920 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 921 (post_truncst node:$val, node:$base, node:$offset), [{ 922 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 923 }]>; 924 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 925 (post_truncst node:$val, node:$base, node:$offset), [{ 926 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 927 }]>; 928 929 // nontemporal store fragments. 930 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr), 931 (store node:$val, node:$ptr), [{ 932 return cast<StoreSDNode>(N)->isNonTemporal(); 933 }]>; 934 935 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 936 (nontemporalstore node:$val, node:$ptr), [{ 937 StoreSDNode *St = cast<StoreSDNode>(N); 938 return St->getAlignment() >= St->getMemoryVT().getStoreSize(); 939 }]>; 940 941 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr), 942 (nontemporalstore node:$val, node:$ptr), [{ 943 StoreSDNode *St = cast<StoreSDNode>(N); 944 return St->getAlignment() < St->getMemoryVT().getStoreSize(); 945 }]>; 946 947 // setcc convenience fragments. 948 def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 949 (setcc node:$lhs, node:$rhs, SETOEQ)>; 950 def setogt : PatFrag<(ops node:$lhs, node:$rhs), 951 (setcc node:$lhs, node:$rhs, SETOGT)>; 952 def setoge : PatFrag<(ops node:$lhs, node:$rhs), 953 (setcc node:$lhs, node:$rhs, SETOGE)>; 954 def setolt : PatFrag<(ops node:$lhs, node:$rhs), 955 (setcc node:$lhs, node:$rhs, SETOLT)>; 956 def setole : PatFrag<(ops node:$lhs, node:$rhs), 957 (setcc node:$lhs, node:$rhs, SETOLE)>; 958 def setone : PatFrag<(ops node:$lhs, node:$rhs), 959 (setcc node:$lhs, node:$rhs, SETONE)>; 960 def seto : PatFrag<(ops node:$lhs, node:$rhs), 961 (setcc node:$lhs, node:$rhs, SETO)>; 962 def setuo : PatFrag<(ops node:$lhs, node:$rhs), 963 (setcc node:$lhs, node:$rhs, SETUO)>; 964 def setueq : PatFrag<(ops node:$lhs, node:$rhs), 965 (setcc node:$lhs, node:$rhs, SETUEQ)>; 966 def setugt : PatFrag<(ops node:$lhs, node:$rhs), 967 (setcc node:$lhs, node:$rhs, SETUGT)>; 968 def setuge : PatFrag<(ops node:$lhs, node:$rhs), 969 (setcc node:$lhs, node:$rhs, SETUGE)>; 970 def setult : PatFrag<(ops node:$lhs, node:$rhs), 971 (setcc node:$lhs, node:$rhs, SETULT)>; 972 def setule : PatFrag<(ops node:$lhs, node:$rhs), 973 (setcc node:$lhs, node:$rhs, SETULE)>; 974 def setune : PatFrag<(ops node:$lhs, node:$rhs), 975 (setcc node:$lhs, node:$rhs, SETUNE)>; 976 def seteq : PatFrag<(ops node:$lhs, node:$rhs), 977 (setcc node:$lhs, node:$rhs, SETEQ)>; 978 def setgt : PatFrag<(ops node:$lhs, node:$rhs), 979 (setcc node:$lhs, node:$rhs, SETGT)>; 980 def setge : PatFrag<(ops node:$lhs, node:$rhs), 981 (setcc node:$lhs, node:$rhs, SETGE)>; 982 def setlt : PatFrag<(ops node:$lhs, node:$rhs), 983 (setcc node:$lhs, node:$rhs, SETLT)>; 984 def setle : PatFrag<(ops node:$lhs, node:$rhs), 985 (setcc node:$lhs, node:$rhs, SETLE)>; 986 def setne : PatFrag<(ops node:$lhs, node:$rhs), 987 (setcc node:$lhs, node:$rhs, SETNE)>; 988 989 def atomic_cmp_swap_8 : 990 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 991 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 992 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 993 }]>; 994 def atomic_cmp_swap_16 : 995 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 996 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 997 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 998 }]>; 999 def atomic_cmp_swap_32 : 1000 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 1001 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 1002 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 1003 }]>; 1004 def atomic_cmp_swap_64 : 1005 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 1006 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 1007 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 1008 }]>; 1009 1010 multiclass binary_atomic_op<SDNode atomic_op> { 1011 def _8 : PatFrag<(ops node:$ptr, node:$val), 1012 (atomic_op node:$ptr, node:$val), [{ 1013 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 1014 }]>; 1015 def _16 : PatFrag<(ops node:$ptr, node:$val), 1016 (atomic_op node:$ptr, node:$val), [{ 1017 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 1018 }]>; 1019 def _32 : PatFrag<(ops node:$ptr, node:$val), 1020 (atomic_op node:$ptr, node:$val), [{ 1021 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 1022 }]>; 1023 def _64 : PatFrag<(ops node:$ptr, node:$val), 1024 (atomic_op node:$ptr, node:$val), [{ 1025 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 1026 }]>; 1027 } 1028 1029 defm atomic_load_add : binary_atomic_op<atomic_load_add>; 1030 defm atomic_swap : binary_atomic_op<atomic_swap>; 1031 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 1032 defm atomic_load_and : binary_atomic_op<atomic_load_and>; 1033 defm atomic_load_or : binary_atomic_op<atomic_load_or>; 1034 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 1035 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 1036 defm atomic_load_min : binary_atomic_op<atomic_load_min>; 1037 defm atomic_load_max : binary_atomic_op<atomic_load_max>; 1038 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 1039 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 1040 defm atomic_store : binary_atomic_op<atomic_store>; 1041 1042 def atomic_load_8 : 1043 PatFrag<(ops node:$ptr), 1044 (atomic_load node:$ptr), [{ 1045 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 1046 }]>; 1047 def atomic_load_16 : 1048 PatFrag<(ops node:$ptr), 1049 (atomic_load node:$ptr), [{ 1050 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 1051 }]>; 1052 def atomic_load_32 : 1053 PatFrag<(ops node:$ptr), 1054 (atomic_load node:$ptr), [{ 1055 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 1056 }]>; 1057 def atomic_load_64 : 1058 PatFrag<(ops node:$ptr), 1059 (atomic_load node:$ptr), [{ 1060 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 1061 }]>; 1062 1063 //===----------------------------------------------------------------------===// 1064 // Selection DAG CONVERT_RNDSAT patterns 1065 1066 def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1067 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1068 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF; 1069 }]>; 1070 1071 def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1072 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1073 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS; 1074 }]>; 1075 1076 def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1077 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1078 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU; 1079 }]>; 1080 1081 def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1082 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1083 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US; 1084 }]>; 1085 1086 def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1087 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1088 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU; 1089 }]>; 1090 1091 def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1092 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1093 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF; 1094 }]>; 1095 1096 def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1097 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1098 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF; 1099 }]>; 1100 1101 def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1102 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1103 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS; 1104 }]>; 1105 1106 def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 1107 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 1108 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU; 1109 }]>; 1110 1111 //===----------------------------------------------------------------------===// 1112 // Selection DAG Pattern Support. 1113 // 1114 // Patterns are what are actually matched against by the target-flavored 1115 // instruction selection DAG. Instructions defined by the target implicitly 1116 // define patterns in most cases, but patterns can also be explicitly added when 1117 // an operation is defined by a sequence of instructions (e.g. loading a large 1118 // immediate value on RISC targets that do not support immediates as large as 1119 // their GPRs). 1120 // 1121 1122 class Pattern<dag patternToMatch, list<dag> resultInstrs> { 1123 dag PatternToMatch = patternToMatch; 1124 list<dag> ResultInstrs = resultInstrs; 1125 list<Predicate> Predicates = []; // See class Instruction in Target.td. 1126 int AddedComplexity = 0; // See class Instruction in Target.td. 1127 } 1128 1129 // Pat - A simple (but common) form of a pattern, which produces a simple result 1130 // not needing a full list. 1131 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 1132 1133 //===----------------------------------------------------------------------===// 1134 // Complex pattern definitions. 1135 // 1136 1137 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code 1138 // in C++. NumOperands is the number of operands returned by the select function; 1139 // SelectFunc is the name of the function used to pattern match the max. pattern; 1140 // RootNodes are the list of possible root nodes of the sub-dags to match. 1141 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 1142 // 1143 class ComplexPattern<ValueType ty, int numops, string fn, 1144 list<SDNode> roots = [], list<SDNodeProperty> props = []> { 1145 ValueType Ty = ty; 1146 int NumOperands = numops; 1147 string SelectFunc = fn; 1148 list<SDNode> RootNodes = roots; 1149 list<SDNodeProperty> Properties = props; 1150 } 1151
