1 //===- AArch64RegisterInfo.cpp - AArch64 Register Information -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the AArch64 implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "AArch64RegisterInfo.h" 16 #include "AArch64FrameLowering.h" 17 #include "AArch64InstrInfo.h" 18 #include "AArch64MachineFunctionInfo.h" 19 #include "AArch64Subtarget.h" 20 #include "MCTargetDesc/AArch64AddressingModes.h" 21 #include "llvm/ADT/BitVector.h" 22 #include "llvm/ADT/Triple.h" 23 #include "llvm/CodeGen/MachineFrameInfo.h" 24 #include "llvm/CodeGen/MachineInstrBuilder.h" 25 #include "llvm/CodeGen/MachineRegisterInfo.h" 26 #include "llvm/CodeGen/RegisterScavenging.h" 27 #include "llvm/IR/Function.h" 28 #include "llvm/Support/CommandLine.h" 29 #include "llvm/Support/raw_ostream.h" 30 #include "llvm/Target/TargetFrameLowering.h" 31 #include "llvm/Target/TargetOptions.h" 32 33 using namespace llvm; 34 35 #define GET_REGINFO_TARGET_DESC 36 #include "AArch64GenRegisterInfo.inc" 37 38 AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT) 39 : AArch64GenRegisterInfo(AArch64::LR), TT(TT) {} 40 41 const MCPhysReg * 42 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 43 assert(MF && "Invalid MachineFunction pointer."); 44 if (MF->getFunction()->getCallingConv() == CallingConv::GHC) 45 // GHC set of callee saved regs is empty as all those regs are 46 // used for passing STG regs around 47 return CSR_AArch64_NoRegs_SaveList; 48 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg) 49 return CSR_AArch64_AllRegs_SaveList; 50 if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS) 51 return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ? 52 CSR_AArch64_CXX_TLS_Darwin_PE_SaveList : 53 CSR_AArch64_CXX_TLS_Darwin_SaveList; 54 else 55 return CSR_AArch64_AAPCS_SaveList; 56 } 57 58 const MCPhysReg *AArch64RegisterInfo::getCalleeSavedRegsViaCopy( 59 const MachineFunction *MF) const { 60 assert(MF && "Invalid MachineFunction pointer."); 61 if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS && 62 MF->getInfo<AArch64FunctionInfo>()->isSplitCSR()) 63 return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList; 64 return nullptr; 65 } 66 67 const uint32_t * 68 AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF, 69 CallingConv::ID CC) const { 70 if (CC == CallingConv::GHC) 71 // This is academic becase all GHC calls are (supposed to be) tail calls 72 return CSR_AArch64_NoRegs_RegMask; 73 if (CC == CallingConv::AnyReg) 74 return CSR_AArch64_AllRegs_RegMask; 75 if (CC == CallingConv::CXX_FAST_TLS) 76 return CSR_AArch64_CXX_TLS_Darwin_RegMask; 77 else 78 return CSR_AArch64_AAPCS_RegMask; 79 } 80 81 const uint32_t *AArch64RegisterInfo::getTLSCallPreservedMask() const { 82 if (TT.isOSDarwin()) 83 return CSR_AArch64_TLS_Darwin_RegMask; 84 85 assert(TT.isOSBinFormatELF() && "only expect Darwin or ELF TLS"); 86 return CSR_AArch64_TLS_ELF_RegMask; 87 } 88 89 const uint32_t * 90 AArch64RegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF, 91 CallingConv::ID CC) const { 92 // This should return a register mask that is the same as that returned by 93 // getCallPreservedMask but that additionally preserves the register used for 94 // the first i64 argument (which must also be the register used to return a 95 // single i64 return value) 96 // 97 // In case that the calling convention does not use the same register for 98 // both, the function should return NULL (does not currently apply) 99 assert(CC != CallingConv::GHC && "should not be GHC calling convention."); 100 return CSR_AArch64_AAPCS_ThisReturn_RegMask; 101 } 102 103 BitVector 104 AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const { 105 const AArch64FrameLowering *TFI = getFrameLowering(MF); 106 107 // FIXME: avoid re-calculating this every time. 108 BitVector Reserved(getNumRegs()); 109 Reserved.set(AArch64::SP); 110 Reserved.set(AArch64::XZR); 111 Reserved.set(AArch64::WSP); 112 Reserved.set(AArch64::WZR); 113 114 if (TFI->hasFP(MF) || TT.isOSDarwin()) { 115 Reserved.set(AArch64::FP); 116 Reserved.set(AArch64::W29); 117 } 118 119 if (MF.getSubtarget<AArch64Subtarget>().isX18Reserved()) { 120 Reserved.set(AArch64::X18); // Platform register 121 Reserved.set(AArch64::W18); 122 } 123 124 if (hasBasePointer(MF)) { 125 Reserved.set(AArch64::X19); 126 Reserved.set(AArch64::W19); 127 } 128 129 return Reserved; 130 } 131 132 bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF, 133 unsigned Reg) const { 134 const AArch64FrameLowering *TFI = getFrameLowering(MF); 135 136 switch (Reg) { 137 default: 138 break; 139 case AArch64::SP: 140 case AArch64::XZR: 141 case AArch64::WSP: 142 case AArch64::WZR: 143 return true; 144 case AArch64::X18: 145 case AArch64::W18: 146 return MF.getSubtarget<AArch64Subtarget>().isX18Reserved(); 147 case AArch64::FP: 148 case AArch64::W29: 149 return TFI->hasFP(MF) || TT.isOSDarwin(); 150 case AArch64::W19: 151 case AArch64::X19: 152 return hasBasePointer(MF); 153 } 154 155 return false; 156 } 157 158 const TargetRegisterClass * 159 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF, 160 unsigned Kind) const { 161 return &AArch64::GPR64RegClass; 162 } 163 164 const TargetRegisterClass * 165 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 166 if (RC == &AArch64::CCRRegClass) 167 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV. 168 return RC; 169 } 170 171 unsigned AArch64RegisterInfo::getBaseRegister() const { return AArch64::X19; } 172 173 bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const { 174 const MachineFrameInfo *MFI = MF.getFrameInfo(); 175 176 // In the presence of variable sized objects, if the fixed stack size is 177 // large enough that referencing from the FP won't result in things being 178 // in range relatively often, we can use a base pointer to allow access 179 // from the other direction like the SP normally works. 180 // Furthermore, if both variable sized objects are present, and the 181 // stack needs to be dynamically re-aligned, the base pointer is the only 182 // reliable way to reference the locals. 183 if (MFI->hasVarSizedObjects()) { 184 if (needsStackRealignment(MF)) 185 return true; 186 // Conservatively estimate whether the negative offset from the frame 187 // pointer will be sufficient to reach. If a function has a smallish 188 // frame, it's less likely to have lots of spills and callee saved 189 // space, so it's all more likely to be within range of the frame pointer. 190 // If it's wrong, we'll materialize the constant and still get to the 191 // object; it's just suboptimal. Negative offsets use the unscaled 192 // load/store instructions, which have a 9-bit signed immediate. 193 if (MFI->getLocalFrameSize() < 256) 194 return false; 195 return true; 196 } 197 198 return false; 199 } 200 201 unsigned 202 AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const { 203 const AArch64FrameLowering *TFI = getFrameLowering(MF); 204 return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP; 205 } 206 207 bool AArch64RegisterInfo::requiresRegisterScavenging( 208 const MachineFunction &MF) const { 209 return true; 210 } 211 212 bool AArch64RegisterInfo::requiresVirtualBaseRegisters( 213 const MachineFunction &MF) const { 214 return true; 215 } 216 217 bool 218 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const { 219 const MachineFrameInfo *MFI = MF.getFrameInfo(); 220 // AArch64FrameLowering::resolveFrameIndexReference() can always fall back 221 // to the stack pointer, so only put the emergency spill slot next to the 222 // FP when there's no better way to access it (SP or base pointer). 223 return MFI->hasVarSizedObjects() && !hasBasePointer(MF); 224 } 225 226 bool AArch64RegisterInfo::requiresFrameIndexScavenging( 227 const MachineFunction &MF) const { 228 return true; 229 } 230 231 bool 232 AArch64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const { 233 const MachineFrameInfo *MFI = MF.getFrameInfo(); 234 // Only consider eliminating leaf frames. 235 if (MFI->hasCalls() || (MF.getTarget().Options.DisableFramePointerElim(MF) && 236 MFI->adjustsStack())) 237 return true; 238 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken(); 239 } 240 241 /// needsFrameBaseReg - Returns true if the instruction's frame index 242 /// reference would be better served by a base register other than FP 243 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 244 /// references it should create new base registers for. 245 bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI, 246 int64_t Offset) const { 247 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) 248 assert(i < MI->getNumOperands() && 249 "Instr doesn't have FrameIndex operand!"); 250 251 // It's the load/store FI references that cause issues, as it can be difficult 252 // to materialize the offset if it won't fit in the literal field. Estimate 253 // based on the size of the local frame and some conservative assumptions 254 // about the rest of the stack frame (note, this is pre-regalloc, so 255 // we don't know everything for certain yet) whether this offset is likely 256 // to be out of range of the immediate. Return true if so. 257 258 // We only generate virtual base registers for loads and stores, so 259 // return false for everything else. 260 if (!MI->mayLoad() && !MI->mayStore()) 261 return false; 262 263 // Without a virtual base register, if the function has variable sized 264 // objects, all fixed-size local references will be via the frame pointer, 265 // Approximate the offset and see if it's legal for the instruction. 266 // Note that the incoming offset is based on the SP value at function entry, 267 // so it'll be negative. 268 MachineFunction &MF = *MI->getParent()->getParent(); 269 const AArch64FrameLowering *TFI = getFrameLowering(MF); 270 MachineFrameInfo *MFI = MF.getFrameInfo(); 271 272 // Estimate an offset from the frame pointer. 273 // Conservatively assume all GPR callee-saved registers get pushed. 274 // FP, LR, X19-X28, D8-D15. 64-bits each. 275 int64_t FPOffset = Offset - 16 * 20; 276 // Estimate an offset from the stack pointer. 277 // The incoming offset is relating to the SP at the start of the function, 278 // but when we access the local it'll be relative to the SP after local 279 // allocation, so adjust our SP-relative offset by that allocation size. 280 Offset += MFI->getLocalFrameSize(); 281 // Assume that we'll have at least some spill slots allocated. 282 // FIXME: This is a total SWAG number. We should run some statistics 283 // and pick a real one. 284 Offset += 128; // 128 bytes of spill slots 285 286 // If there is a frame pointer, try using it. 287 // The FP is only available if there is no dynamic realignment. We 288 // don't know for sure yet whether we'll need that, so we guess based 289 // on whether there are any local variables that would trigger it. 290 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, AArch64::FP, FPOffset)) 291 return false; 292 293 // If we can reference via the stack pointer or base pointer, try that. 294 // FIXME: This (and the code that resolves the references) can be improved 295 // to only disallow SP relative references in the live range of 296 // the VLA(s). In practice, it's unclear how much difference that 297 // would make, but it may be worth doing. 298 if (isFrameOffsetLegal(MI, AArch64::SP, Offset)) 299 return false; 300 301 // The offset likely isn't legal; we want to allocate a virtual base register. 302 return true; 303 } 304 305 bool AArch64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 306 unsigned BaseReg, 307 int64_t Offset) const { 308 assert(Offset <= INT_MAX && "Offset too big to fit in int."); 309 assert(MI && "Unable to get the legal offset for nil instruction."); 310 int SaveOffset = Offset; 311 return isAArch64FrameOffsetLegal(*MI, SaveOffset) & AArch64FrameOffsetIsLegal; 312 } 313 314 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx 315 /// at the beginning of the basic block. 316 void AArch64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB, 317 unsigned BaseReg, 318 int FrameIdx, 319 int64_t Offset) const { 320 MachineBasicBlock::iterator Ins = MBB->begin(); 321 DebugLoc DL; // Defaults to "unknown" 322 if (Ins != MBB->end()) 323 DL = Ins->getDebugLoc(); 324 const MachineFunction &MF = *MBB->getParent(); 325 const AArch64InstrInfo *TII = 326 MF.getSubtarget<AArch64Subtarget>().getInstrInfo(); 327 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri); 328 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 329 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF)); 330 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0); 331 332 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 333 .addFrameIndex(FrameIdx) 334 .addImm(Offset) 335 .addImm(Shifter); 336 } 337 338 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 339 int64_t Offset) const { 340 int Off = Offset; // ARM doesn't need the general 64-bit offsets 341 unsigned i = 0; 342 343 while (!MI.getOperand(i).isFI()) { 344 ++i; 345 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 346 } 347 const MachineFunction *MF = MI.getParent()->getParent(); 348 const AArch64InstrInfo *TII = 349 MF->getSubtarget<AArch64Subtarget>().getInstrInfo(); 350 bool Done = rewriteAArch64FrameIndex(MI, i, BaseReg, Off, TII); 351 assert(Done && "Unable to resolve frame index!"); 352 (void)Done; 353 } 354 355 void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 356 int SPAdj, unsigned FIOperandNum, 357 RegScavenger *RS) const { 358 assert(SPAdj == 0 && "Unexpected"); 359 360 MachineInstr &MI = *II; 361 MachineBasicBlock &MBB = *MI.getParent(); 362 MachineFunction &MF = *MBB.getParent(); 363 const AArch64InstrInfo *TII = 364 MF.getSubtarget<AArch64Subtarget>().getInstrInfo(); 365 const AArch64FrameLowering *TFI = getFrameLowering(MF); 366 367 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 368 unsigned FrameReg; 369 int Offset; 370 371 // Special handling of dbg_value, stackmap and patchpoint instructions. 372 if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP || 373 MI.getOpcode() == TargetOpcode::PATCHPOINT) { 374 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg, 375 /*PreferFP=*/true); 376 Offset += MI.getOperand(FIOperandNum + 1).getImm(); 377 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/); 378 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 379 return; 380 } 381 382 // Modify MI as necessary to handle as much of 'Offset' as possible 383 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg); 384 if (rewriteAArch64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII)) 385 return; 386 387 assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) && 388 "Emergency spill slot is out of reach"); 389 390 // If we get here, the immediate doesn't fit into the instruction. We folded 391 // as much as possible above. Handle the rest, providing a register that is 392 // SP+LargeImm. 393 unsigned ScratchReg = 394 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); 395 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII); 396 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true); 397 } 398 399 namespace llvm { 400 401 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 402 MachineFunction &MF) const { 403 const AArch64FrameLowering *TFI = getFrameLowering(MF); 404 405 switch (RC->getID()) { 406 default: 407 return 0; 408 case AArch64::GPR32RegClassID: 409 case AArch64::GPR32spRegClassID: 410 case AArch64::GPR32allRegClassID: 411 case AArch64::GPR64spRegClassID: 412 case AArch64::GPR64allRegClassID: 413 case AArch64::GPR64RegClassID: 414 case AArch64::GPR32commonRegClassID: 415 case AArch64::GPR64commonRegClassID: 416 return 32 - 1 // XZR/SP 417 - (TFI->hasFP(MF) || TT.isOSDarwin()) // FP 418 - MF.getSubtarget<AArch64Subtarget>() 419 .isX18Reserved() // X18 reserved as platform register 420 - hasBasePointer(MF); // X19 421 case AArch64::FPR8RegClassID: 422 case AArch64::FPR16RegClassID: 423 case AArch64::FPR32RegClassID: 424 case AArch64::FPR64RegClassID: 425 case AArch64::FPR128RegClassID: 426 return 32; 427 428 case AArch64::DDRegClassID: 429 case AArch64::DDDRegClassID: 430 case AArch64::DDDDRegClassID: 431 case AArch64::QQRegClassID: 432 case AArch64::QQQRegClassID: 433 case AArch64::QQQQRegClassID: 434 return 32; 435 436 case AArch64::FPR128_loRegClassID: 437 return 16; 438 } 439 } 440 441 } // namespace llvm 442
