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      1 //===-- AMDGPU.td - AMDGPU Tablegen files ------------------*- tablegen -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 include "llvm/Target/Target.td"
     11 
     12 //===----------------------------------------------------------------------===//
     13 // Subtarget Features
     14 //===----------------------------------------------------------------------===//
     15 
     16 // Debugging Features
     17 
     18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
     19         "DumpCode",
     20         "true",
     21         "Dump MachineInstrs in the CodeEmitter">;
     22 
     23 def FeatureDumpCodeLower : SubtargetFeature <"dumpcode",
     24         "DumpCode",
     25         "true",
     26         "Dump MachineInstrs in the CodeEmitter">;
     27 
     28 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
     29         "EnableIRStructurizer",
     30         "false",
     31         "Disable IR Structurizer">;
     32 
     33 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
     34         "EnablePromoteAlloca",
     35         "true",
     36         "Enable promote alloca pass">;
     37 
     38 // Target features
     39 
     40 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
     41         "EnableIfCvt",
     42         "false",
     43         "Disable the if conversion pass">;
     44 
     45 def FeatureFP64 : SubtargetFeature<"fp64",
     46         "FP64",
     47         "true",
     48         "Enable double precision operations">;
     49 
     50 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
     51         "FP64Denormals",
     52         "true",
     53         "Enable double precision denormal handling",
     54         [FeatureFP64]>;
     55 
     56 def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
     57         "FastFMAF32",
     58         "true",
     59         "Assuming f32 fma is at least as fast as mul + add",
     60         []>;
     61 
     62 // Some instructions do not support denormals despite this flag. Using
     63 // fp32 denormals also causes instructions to run at the double
     64 // precision rate for the device.
     65 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
     66         "FP32Denormals",
     67         "true",
     68         "Enable single precision denormal handling">;
     69 
     70 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
     71         "Is64bit",
     72         "true",
     73         "Specify if 64-bit addressing should be used">;
     74 
     75 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
     76         "R600ALUInst",
     77         "false",
     78         "Older version of ALU instructions encoding">;
     79 
     80 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
     81         "HasVertexCache",
     82         "true",
     83         "Specify use of dedicated vertex cache">;
     84 
     85 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
     86         "CaymanISA",
     87         "true",
     88         "Use Cayman ISA">;
     89 
     90 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
     91         "CFALUBug",
     92         "true",
     93         "GPU has CF_ALU bug">;
     94 
     95 // XXX - This should probably be removed once enabled by default
     96 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
     97         "EnableLoadStoreOpt",
     98         "true",
     99         "Enable SI load/store optimizer pass">;
    100 
    101 // Performance debugging feature. Allow using DS instruction immediate
    102 // offsets even if the base pointer can't be proven to be base. On SI,
    103 // base pointer values that won't give the same result as a 16-bit add
    104 // are not safe to fold, but this will override the conservative test
    105 // for the base pointer.
    106 def FeatureEnableUnsafeDSOffsetFolding : SubtargetFeature <"unsafe-ds-offset-folding",
    107         "EnableUnsafeDSOffsetFolding",
    108         "true",
    109         "Force using DS instruction immediate offsets on SI">;
    110 
    111 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
    112         "FlatAddressSpace",
    113         "true",
    114         "Support flat address space">;
    115 
    116 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
    117         "EnableVGPRSpilling",
    118         "true",
    119         "Enable spilling of VGPRs to scratch memory">;
    120 
    121 def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
    122         "SGPRInitBug",
    123         "true",
    124         "VI SGPR initilization bug requiring a fixed SGPR allocation size">;
    125 
    126 def FeatureEnableHugeScratchBuffer : SubtargetFeature<"huge-scratch-buffer",
    127         "EnableHugeScratchBuffer",
    128         "true",
    129         "Enable scratch buffer sizes greater than 128 GB">;
    130 
    131 class SubtargetFeatureFetchLimit <string Value> :
    132                           SubtargetFeature <"fetch"#Value,
    133         "TexVTXClauseSize",
    134         Value,
    135         "Limit the maximum number of fetches in a clause to "#Value>;
    136 
    137 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
    138 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
    139 
    140 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
    141         "wavefrontsize"#Value,
    142         "WavefrontSize",
    143         !cast<string>(Value),
    144         "The number of threads per wavefront">;
    145 
    146 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
    147 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
    148 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
    149 
    150 class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
    151       "ldsbankcount"#Value,
    152       "LDSBankCount",
    153       !cast<string>(Value),
    154       "The number of LDS banks per compute unit.">;
    155 
    156 def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
    157 def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
    158 
    159 class SubtargetFeatureISAVersion <int Major, int Minor, int Stepping>
    160                                  : SubtargetFeature <
    161       "isaver"#Major#"."#Minor#"."#Stepping,
    162       "IsaVersion",
    163       "ISAVersion"#Major#"_"#Minor#"_"#Stepping,
    164       "Instruction set version number"
    165 >;
    166 
    167 def FeatureISAVersion7_0_0 : SubtargetFeatureISAVersion <7,0,0>;
    168 def FeatureISAVersion7_0_1 : SubtargetFeatureISAVersion <7,0,1>;
    169 def FeatureISAVersion8_0_0 : SubtargetFeatureISAVersion <8,0,0>;
    170 def FeatureISAVersion8_0_1 : SubtargetFeatureISAVersion <8,0,1>;
    171 
    172 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
    173         "localmemorysize"#Value,
    174         "LocalMemorySize",
    175         !cast<string>(Value),
    176         "The size of local memory in bytes">;
    177 
    178 def FeatureGCN : SubtargetFeature<"gcn",
    179         "IsGCN",
    180         "true",
    181         "GCN or newer GPU">;
    182 
    183 def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
    184         "GCN1Encoding",
    185         "true",
    186         "Encoding format for SI and CI">;
    187 
    188 def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
    189         "GCN3Encoding",
    190         "true",
    191         "Encoding format for VI">;
    192 
    193 def FeatureCIInsts : SubtargetFeature<"ci-insts",
    194         "CIInsts",
    195         "true",
    196         "Additional intstructions for CI+">;
    197 
    198 // Dummy feature used to disable assembler instructions.
    199 def FeatureDisable : SubtargetFeature<"",
    200                                       "FeatureDisable","true",
    201                                       "Dummy feature to disable assembler"
    202                                       " instructions">;
    203 
    204 class SubtargetFeatureGeneration <string Value,
    205                                   list<SubtargetFeature> Implies> :
    206         SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
    207                           Value#" GPU generation", Implies>;
    208 
    209 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
    210 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
    211 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
    212 
    213 def FeatureR600 : SubtargetFeatureGeneration<"R600",
    214         [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
    215 
    216 def FeatureR700 : SubtargetFeatureGeneration<"R700",
    217         [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
    218 
    219 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
    220         [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
    221 
    222 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
    223         [FeatureFetchLimit16, FeatureWavefrontSize64,
    224          FeatureLocalMemorySize32768]
    225 >;
    226 
    227 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
    228         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
    229          FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
    230          FeatureLDSBankCount32]>;
    231 
    232 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
    233         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
    234          FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
    235          FeatureGCN1Encoding, FeatureCIInsts]>;
    236 
    237 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
    238         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
    239          FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
    240          FeatureGCN3Encoding, FeatureCIInsts, FeatureLDSBankCount32]>;
    241 
    242 //===----------------------------------------------------------------------===//
    243 
    244 def AMDGPUInstrInfo : InstrInfo {
    245   let guessInstructionProperties = 1;
    246   let noNamedPositionallyEncodedOperands = 1;
    247 }
    248 
    249 def AMDGPUAsmParser : AsmParser {
    250   // Some of the R600 registers have the same name, so this crashes.
    251   // For example T0_XYZW and T0_XY both have the asm name T0.
    252   let ShouldEmitMatchRegisterName = 0;
    253 }
    254 
    255 def AMDGPU : Target {
    256   // Pull in Instruction Info:
    257   let InstructionSet = AMDGPUInstrInfo;
    258   let AssemblyParsers = [AMDGPUAsmParser];
    259 }
    260 
    261 // Dummy Instruction itineraries for pseudo instructions
    262 def ALU_NULL : FuncUnit;
    263 def NullALU : InstrItinClass;
    264 
    265 //===----------------------------------------------------------------------===//
    266 // Predicate helper class
    267 //===----------------------------------------------------------------------===//
    268 
    269 def TruePredicate : Predicate<"true">;
    270 def isSICI : Predicate<
    271   "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
    272   "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
    273 >, AssemblerPredicate<"FeatureGCN1Encoding">;
    274 
    275 class PredicateControl {
    276   Predicate SubtargetPredicate;
    277   Predicate SIAssemblerPredicate = isSICI;
    278   list<Predicate> AssemblerPredicates = [];
    279   Predicate AssemblerPredicate = TruePredicate;
    280   list<Predicate> OtherPredicates = [];
    281   list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
    282                                             AssemblerPredicates,
    283                                             OtherPredicates);
    284 }
    285 
    286 // Include AMDGPU TD files
    287 include "R600Schedule.td"
    288 include "SISchedule.td"
    289 include "Processors.td"
    290 include "AMDGPUInstrInfo.td"
    291 include "AMDGPUIntrinsics.td"
    292 include "AMDGPURegisterInfo.td"
    293 include "AMDGPUInstructions.td"
    294 include "AMDGPUCallingConv.td"
    295