1 //===---- AMDCallingConv.td - Calling Conventions for Radeon GPUs ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This describes the calling conventions for the AMD Radeon GPUs. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // Inversion of CCIfInReg 15 class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {} 16 17 // Calling convention for SI 18 def CC_SI : CallingConv<[ 19 20 CCIfInReg<CCIfType<[f32, i32] , CCAssignToReg<[ 21 SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7, 22 SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15, 23 SGPR16, SGPR17, SGPR18, SGPR19, SGPR20, SGPR21 24 ]>>>, 25 26 CCIfInReg<CCIfType<[i64] , CCAssignToRegWithShadow< 27 [ SGPR0, SGPR2, SGPR4, SGPR6, SGPR8, SGPR10, SGPR12, SGPR14 ], 28 [ SGPR1, SGPR3, SGPR5, SGPR7, SGPR9, SGPR11, SGPR13, SGPR15 ] 29 >>>, 30 31 CCIfNotInReg<CCIfType<[f32, i32] , CCAssignToReg<[ 32 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7, 33 VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15, 34 VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23, 35 VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31 36 ]>>>, 37 38 CCIfByVal<CCIfType<[i64] , CCAssignToRegWithShadow< 39 [ SGPR0, SGPR2, SGPR4, SGPR6, SGPR8, SGPR10, SGPR12, SGPR14 ], 40 [ SGPR1, SGPR3, SGPR5, SGPR7, SGPR9, SGPR11, SGPR13, SGPR15 ] 41 >>> 42 43 ]>; 44 45 // Calling convention for R600 46 def CC_R600 : CallingConv<[ 47 CCIfInReg<CCIfType<[v4f32, v4i32] , CCAssignToReg<[ 48 T0_XYZW, T1_XYZW, T2_XYZW, T3_XYZW, T4_XYZW, T5_XYZW, T6_XYZW, T7_XYZW, 49 T8_XYZW, T9_XYZW, T10_XYZW, T11_XYZW, T12_XYZW, T13_XYZW, T14_XYZW, T15_XYZW, 50 T16_XYZW, T17_XYZW, T18_XYZW, T19_XYZW, T20_XYZW, T21_XYZW, T22_XYZW, 51 T23_XYZW, T24_XYZW, T25_XYZW, T26_XYZW, T27_XYZW, T28_XYZW, T29_XYZW, 52 T30_XYZW, T31_XYZW, T32_XYZW 53 ]>>> 54 ]>; 55 56 // Calling convention for compute kernels 57 def CC_AMDGPU_Kernel : CallingConv<[ 58 CCCustom<"allocateStack"> 59 ]>; 60 61 def CC_AMDGPU : CallingConv<[ 62 CCIf<"static_cast<const AMDGPUSubtarget&>" 63 "(State.getMachineFunction().getSubtarget()).getGeneration() >=" 64 "AMDGPUSubtarget::SOUTHERN_ISLANDS && " 65 "State.getMachineFunction().getInfo<SIMachineFunctionInfo>()" 66 "->getShaderType() == ShaderType::COMPUTE", 67 CCDelegateTo<CC_AMDGPU_Kernel>>, 68 CCIf<"static_cast<const AMDGPUSubtarget&>" 69 "(State.getMachineFunction().getSubtarget()).getGeneration() < " 70 "AMDGPUSubtarget::SOUTHERN_ISLANDS && " 71 "State.getMachineFunction().getInfo<R600MachineFunctionInfo>()" 72 "->getShaderType() == ShaderType::COMPUTE", 73 CCDelegateTo<CC_AMDGPU_Kernel>>, 74 CCIf<"static_cast<const AMDGPUSubtarget&>" 75 "(State.getMachineFunction().getSubtarget()).getGeneration() >= " 76 "AMDGPUSubtarget::SOUTHERN_ISLANDS", 77 CCDelegateTo<CC_SI>>, 78 CCIf<"static_cast<const AMDGPUSubtarget&>" 79 "(State.getMachineFunction().getSubtarget()).getGeneration() < " 80 "AMDGPUSubtarget::SOUTHERN_ISLANDS", 81 CCDelegateTo<CC_R600>> 82 ]>; 83
