1 //===-- CaymanInstructions.td - CM Instruction defs -------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // TableGen definitions for instructions which are available only on Cayman 11 // family GPUs. 12 // 13 //===----------------------------------------------------------------------===// 14 15 def isCayman : Predicate<"Subtarget->hasCaymanISA()">; 16 17 //===----------------------------------------------------------------------===// 18 // Cayman Instructions 19 //===----------------------------------------------------------------------===// 20 21 let Predicates = [isCayman] in { 22 23 def MULADD_INT24_cm : R600_3OP <0x08, "MULADD_INT24", 24 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))], VecALU 25 >; 26 def MUL_INT24_cm : R600_2OP <0x5B, "MUL_INT24", 27 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))], VecALU 28 >; 29 30 def : IMad24Pat<MULADD_INT24_cm>; 31 32 let isVector = 1 in { 33 34 def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>; 35 36 def MULLO_INT_cm : MULLO_INT_Common<0x8F>; 37 def MULHI_INT_cm : MULHI_INT_Common<0x90>; 38 def MULLO_UINT_cm : MULLO_UINT_Common<0x91>; 39 def MULHI_UINT_cm : MULHI_UINT_Common<0x92>; 40 def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>; 41 def EXP_IEEE_cm : EXP_IEEE_Common<0x81>; 42 def LOG_IEEE_cm : LOG_IEEE_Common<0x83>; 43 def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>; 44 def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>; 45 def SIN_cm : SIN_Common<0x8D>; 46 def COS_cm : COS_Common<0x8E>; 47 } // End isVector = 1 48 49 def : RsqPat<RECIPSQRT_IEEE_cm, f32>; 50 51 def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>; 52 53 defm DIV_cm : DIV_Common<RECIP_IEEE_cm>; 54 defm : Expand24UBitOps<MULLO_UINT_cm, ADD_INT>; 55 56 // RECIP_UINT emulation for Cayman 57 // The multiplication scales from [0,1] to the unsigned integer range 58 def : Pat < 59 (AMDGPUurecip i32:$src0), 60 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)), 61 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1))) 62 >; 63 64 def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> { 65 let ADDR = 0; 66 let POP_COUNT = 0; 67 let COUNT = 0; 68 } 69 70 71 def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>; 72 73 class RAT_STORE_DWORD <RegisterClass rc, ValueType vt, bits<4> mask> : 74 CF_MEM_RAT_CACHELESS <0x14, 0, mask, 75 (ins rc:$rw_gpr, R600_TReg32_X:$index_gpr), 76 "STORE_DWORD $rw_gpr, $index_gpr", 77 [(global_store vt:$rw_gpr, i32:$index_gpr)]> { 78 let eop = 0; // This bit is not used on Cayman. 79 } 80 81 def RAT_STORE_DWORD32 : RAT_STORE_DWORD <R600_TReg32_X, i32, 0x1>; 82 def RAT_STORE_DWORD64 : RAT_STORE_DWORD <R600_Reg64, v2i32, 0x3>; 83 def RAT_STORE_DWORD128 : RAT_STORE_DWORD <R600_Reg128, v4i32, 0xf>; 84 85 def RAT_STORE_TYPED_cm: CF_MEM_RAT_STORE_TYPED<0> { 86 let eop = 0; // This bit is not used on Cayman. 87 } 88 89 class VTX_READ_cm <string name, bits<8> buffer_id, dag outs, list<dag> pattern> 90 : VTX_WORD0_cm, VTX_READ<name, buffer_id, outs, pattern> { 91 92 // Static fields 93 let VC_INST = 0; 94 let FETCH_TYPE = 2; 95 let FETCH_WHOLE_QUAD = 0; 96 let BUFFER_ID = buffer_id; 97 let SRC_REL = 0; 98 // XXX: We can infer this field based on the SRC_GPR. This would allow us 99 // to store vertex addresses in any channel, not just X. 100 let SRC_SEL_X = 0; 101 let SRC_SEL_Y = 0; 102 let STRUCTURED_READ = 0; 103 let LDS_REQ = 0; 104 let COALESCED_READ = 0; 105 106 let Inst{31-0} = Word0; 107 } 108 109 class VTX_READ_8_cm <bits<8> buffer_id, list<dag> pattern> 110 : VTX_READ_cm <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id, 111 (outs R600_TReg32_X:$dst_gpr), pattern> { 112 113 let DST_SEL_X = 0; 114 let DST_SEL_Y = 7; // Masked 115 let DST_SEL_Z = 7; // Masked 116 let DST_SEL_W = 7; // Masked 117 let DATA_FORMAT = 1; // FMT_8 118 } 119 120 class VTX_READ_16_cm <bits<8> buffer_id, list<dag> pattern> 121 : VTX_READ_cm <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id, 122 (outs R600_TReg32_X:$dst_gpr), pattern> { 123 let DST_SEL_X = 0; 124 let DST_SEL_Y = 7; // Masked 125 let DST_SEL_Z = 7; // Masked 126 let DST_SEL_W = 7; // Masked 127 let DATA_FORMAT = 5; // FMT_16 128 129 } 130 131 class VTX_READ_32_cm <bits<8> buffer_id, list<dag> pattern> 132 : VTX_READ_cm <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id, 133 (outs R600_TReg32_X:$dst_gpr), pattern> { 134 135 let DST_SEL_X = 0; 136 let DST_SEL_Y = 7; // Masked 137 let DST_SEL_Z = 7; // Masked 138 let DST_SEL_W = 7; // Masked 139 let DATA_FORMAT = 0xD; // COLOR_32 140 141 // This is not really necessary, but there were some GPU hangs that appeared 142 // to be caused by ALU instructions in the next instruction group that wrote 143 // to the $src_gpr registers of the VTX_READ. 144 // e.g. 145 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24 146 // %T2_X<def> = MOV %ZERO 147 //Adding this constraint prevents this from happening. 148 let Constraints = "$src_gpr.ptr = $dst_gpr"; 149 } 150 151 class VTX_READ_64_cm <bits<8> buffer_id, list<dag> pattern> 152 : VTX_READ_cm <"VTX_READ_64 $dst_gpr, $src_gpr", buffer_id, 153 (outs R600_Reg64:$dst_gpr), pattern> { 154 155 let DST_SEL_X = 0; 156 let DST_SEL_Y = 1; 157 let DST_SEL_Z = 7; 158 let DST_SEL_W = 7; 159 let DATA_FORMAT = 0x1D; // COLOR_32_32 160 } 161 162 class VTX_READ_128_cm <bits<8> buffer_id, list<dag> pattern> 163 : VTX_READ_cm <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id, 164 (outs R600_Reg128:$dst_gpr), pattern> { 165 166 let DST_SEL_X = 0; 167 let DST_SEL_Y = 1; 168 let DST_SEL_Z = 2; 169 let DST_SEL_W = 3; 170 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 171 172 // XXX: Need to force VTX_READ_128 instructions to write to the same register 173 // that holds its buffer address to avoid potential hangs. We can't use 174 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst 175 // registers are different sizes. 176 } 177 178 //===----------------------------------------------------------------------===// 179 // VTX Read from parameter memory space 180 //===----------------------------------------------------------------------===// 181 def VTX_READ_PARAM_8_cm : VTX_READ_8_cm <0, 182 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))] 183 >; 184 185 def VTX_READ_PARAM_16_cm : VTX_READ_16_cm <0, 186 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))] 187 >; 188 189 def VTX_READ_PARAM_32_cm : VTX_READ_32_cm <0, 190 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 191 >; 192 193 def VTX_READ_PARAM_64_cm : VTX_READ_64_cm <0, 194 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 195 >; 196 197 def VTX_READ_PARAM_128_cm : VTX_READ_128_cm <0, 198 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 199 >; 200 201 //===----------------------------------------------------------------------===// 202 // VTX Read from global memory space 203 //===----------------------------------------------------------------------===// 204 205 // 8-bit reads 206 def VTX_READ_GLOBAL_8_cm : VTX_READ_8_cm <1, 207 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))] 208 >; 209 210 def VTX_READ_GLOBAL_16_cm : VTX_READ_16_cm <1, 211 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))] 212 >; 213 214 // 32-bit reads 215 def VTX_READ_GLOBAL_32_cm : VTX_READ_32_cm <1, 216 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 217 >; 218 219 // 64-bit reads 220 def VTX_READ_GLOBAL_64_cm : VTX_READ_64_cm <1, 221 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 222 >; 223 224 // 128-bit reads 225 def VTX_READ_GLOBAL_128_cm : VTX_READ_128_cm <1, 226 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 227 >; 228 229 } // End isCayman 230 231
