1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief SI DAG Lowering interface definition 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_R600_SIISELLOWERING_H 16 #define LLVM_LIB_TARGET_R600_SIISELLOWERING_H 17 18 #include "AMDGPUISelLowering.h" 19 #include "SIInstrInfo.h" 20 21 namespace llvm { 22 23 class SITargetLowering : public AMDGPUTargetLowering { 24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL, 25 SDValue Chain, unsigned Offset, bool Signed) const; 26 SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op, 27 SelectionDAG &DAG) const; 28 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op, 29 SelectionDAG &DAG) const override; 30 31 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, 32 MVT VT, unsigned Offset) const; 33 34 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 35 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 36 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const; 37 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 38 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 39 SDValue LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const; 40 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const; 41 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const; 42 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const; 43 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const; 44 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 45 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const; 46 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 47 48 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const; 49 50 SDValue performUCharToFloatCombine(SDNode *N, 51 DAGCombinerInfo &DCI) const; 52 SDValue performSHLPtrCombine(SDNode *N, 53 unsigned AS, 54 DAGCombinerInfo &DCI) const; 55 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const; 56 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const; 57 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const; 58 59 SDValue performMin3Max3Combine(SDNode *N, DAGCombinerInfo &DCI) const; 60 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; 61 62 bool isLegalFlatAddressingMode(const AddrMode &AM) const; 63 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const; 64 public: 65 SITargetLowering(TargetMachine &tm, const AMDGPUSubtarget &STI); 66 67 bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/, 68 EVT /*VT*/) const override; 69 70 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, 71 unsigned AS) const override; 72 73 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, 74 unsigned Align, 75 bool *IsFast) const override; 76 77 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 78 unsigned SrcAlign, bool IsMemset, 79 bool ZeroMemset, 80 bool MemcpyStrSrc, 81 MachineFunction &MF) const override; 82 83 bool isMemOpUniform(const SDNode *N) const; 84 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 85 86 TargetLoweringBase::LegalizeTypeAction 87 getPreferredVectorAction(EVT VT) const override; 88 89 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 90 Type *Ty) const override; 91 92 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 93 bool isVarArg, 94 const SmallVectorImpl<ISD::InputArg> &Ins, 95 SDLoc DL, SelectionDAG &DAG, 96 SmallVectorImpl<SDValue> &InVals) const override; 97 98 MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI, 99 MachineBasicBlock * BB) const override; 100 bool enableAggressiveFMAFusion(EVT VT) const override; 101 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 102 EVT VT) const override; 103 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override; 104 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 105 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 106 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 107 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; 108 void AdjustInstrPostInstrSelection(MachineInstr *MI, 109 SDNode *Node) const override; 110 111 int32_t analyzeImmediate(const SDNode *N) const; 112 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, 113 unsigned Reg, EVT VT) const override; 114 void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const; 115 116 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, SDLoc DL, SDValue Ptr) const; 117 MachineSDNode *buildRSRC(SelectionDAG &DAG, 118 SDLoc DL, 119 SDValue Ptr, 120 uint32_t RsrcDword1, 121 uint64_t RsrcDword2And3) const; 122 std::pair<unsigned, const TargetRegisterClass *> 123 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 124 StringRef Constraint, MVT VT) const override; 125 ConstraintType getConstraintType(StringRef Constraint) const override; 126 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, SDLoc DL, SDValue V) const; 127 }; 128 129 } // End namespace llvm 130 131 #endif 132
