1 //===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // SI Instruction format definitions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> : 15 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl { 16 17 field bits<1> VM_CNT = 0; 18 field bits<1> EXP_CNT = 0; 19 field bits<1> LGKM_CNT = 0; 20 21 field bits<1> SALU = 0; 22 field bits<1> VALU = 0; 23 24 field bits<1> SOP1 = 0; 25 field bits<1> SOP2 = 0; 26 field bits<1> SOPC = 0; 27 field bits<1> SOPK = 0; 28 field bits<1> SOPP = 0; 29 30 field bits<1> VOP1 = 0; 31 field bits<1> VOP2 = 0; 32 field bits<1> VOP3 = 0; 33 field bits<1> VOPC = 0; 34 35 field bits<1> MUBUF = 0; 36 field bits<1> MTBUF = 0; 37 field bits<1> SMRD = 0; 38 field bits<1> DS = 0; 39 field bits<1> MIMG = 0; 40 field bits<1> FLAT = 0; 41 field bits<1> WQM = 0; 42 field bits<1> VGPRSpill = 0; 43 44 // This bit tells the assembler to use the 32-bit encoding in case it 45 // is unable to infer the encoding from the operands. 46 field bits<1> VOPAsmPrefer32Bit = 0; 47 48 // These need to be kept in sync with the enum in SIInstrFlags. 49 let TSFlags{0} = VM_CNT; 50 let TSFlags{1} = EXP_CNT; 51 let TSFlags{2} = LGKM_CNT; 52 53 let TSFlags{3} = SALU; 54 let TSFlags{4} = VALU; 55 56 let TSFlags{5} = SOP1; 57 let TSFlags{6} = SOP2; 58 let TSFlags{7} = SOPC; 59 let TSFlags{8} = SOPK; 60 let TSFlags{9} = SOPP; 61 62 let TSFlags{10} = VOP1; 63 let TSFlags{11} = VOP2; 64 let TSFlags{12} = VOP3; 65 let TSFlags{13} = VOPC; 66 67 let TSFlags{14} = MUBUF; 68 let TSFlags{15} = MTBUF; 69 let TSFlags{16} = SMRD; 70 let TSFlags{17} = DS; 71 let TSFlags{18} = MIMG; 72 let TSFlags{19} = FLAT; 73 let TSFlags{20} = WQM; 74 let TSFlags{21} = VGPRSpill; 75 let TSFlags{22} = VOPAsmPrefer32Bit; 76 77 let SchedRW = [Write32Bit]; 78 } 79 80 class Enc32 { 81 field bits<32> Inst; 82 int Size = 4; 83 } 84 85 class Enc64 { 86 field bits<64> Inst; 87 int Size = 8; 88 } 89 90 class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">; 91 92 let Uses = [EXEC] in { 93 94 class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> : 95 InstSI <outs, ins, asm, pattern> { 96 97 let mayLoad = 0; 98 let mayStore = 0; 99 let hasSideEffects = 0; 100 let UseNamedOperandTable = 1; 101 let VALU = 1; 102 } 103 104 class VOPCCommon <dag ins, string asm, list<dag> pattern> : 105 VOPAnyCommon <(outs), ins, asm, pattern> { 106 107 let VOPC = 1; 108 let Size = 4; 109 let Defs = [VCC]; 110 } 111 112 class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> : 113 VOPAnyCommon <outs, ins, asm, pattern> { 114 115 let VOP1 = 1; 116 let Size = 4; 117 } 118 119 class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> : 120 VOPAnyCommon <outs, ins, asm, pattern> { 121 122 let VOP2 = 1; 123 let Size = 4; 124 } 125 126 class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> : 127 VOPAnyCommon <outs, ins, asm, pattern> { 128 129 // Using complex patterns gives VOP3 patterns a very high complexity rating, 130 // but standalone patterns are almost always prefered, so we need to adjust the 131 // priority lower. The goal is to use a high number to reduce complexity to 132 // zero (or less than zero). 133 let AddedComplexity = -1000; 134 135 let VOP3 = 1; 136 let VALU = 1; 137 138 let AsmMatchConverter = "cvtVOP3"; 139 let isCodeGenOnly = 0; 140 141 int Size = 8; 142 143 // Because SGPRs may be allowed if there are multiple operands, we 144 // need a post-isel hook to insert copies in order to avoid 145 // violating constant bus requirements. 146 let hasPostISelHook = 1; 147 } 148 149 } // End Uses = [EXEC] 150 151 //===----------------------------------------------------------------------===// 152 // Scalar operations 153 //===----------------------------------------------------------------------===// 154 155 class SOP1e <bits<8> op> : Enc32 { 156 bits<7> sdst; 157 bits<8> ssrc0; 158 159 let Inst{7-0} = ssrc0; 160 let Inst{15-8} = op; 161 let Inst{22-16} = sdst; 162 let Inst{31-23} = 0x17d; //encoding; 163 } 164 165 class SOP2e <bits<7> op> : Enc32 { 166 bits<7> sdst; 167 bits<8> ssrc0; 168 bits<8> ssrc1; 169 170 let Inst{7-0} = ssrc0; 171 let Inst{15-8} = ssrc1; 172 let Inst{22-16} = sdst; 173 let Inst{29-23} = op; 174 let Inst{31-30} = 0x2; // encoding 175 } 176 177 class SOPCe <bits<7> op> : Enc32 { 178 bits<8> ssrc0; 179 bits<8> ssrc1; 180 181 let Inst{7-0} = ssrc0; 182 let Inst{15-8} = ssrc1; 183 let Inst{22-16} = op; 184 let Inst{31-23} = 0x17e; 185 } 186 187 class SOPKe <bits<5> op> : Enc32 { 188 bits <7> sdst; 189 bits <16> simm16; 190 191 let Inst{15-0} = simm16; 192 let Inst{22-16} = sdst; 193 let Inst{27-23} = op; 194 let Inst{31-28} = 0xb; //encoding 195 } 196 197 class SOPK64e <bits<5> op> : Enc64 { 198 bits <7> sdst = 0; 199 bits <16> simm16; 200 bits <32> imm; 201 202 let Inst{15-0} = simm16; 203 let Inst{22-16} = sdst; 204 let Inst{27-23} = op; 205 let Inst{31-28} = 0xb; 206 207 let Inst{63-32} = imm; 208 } 209 210 class SOPPe <bits<7> op> : Enc32 { 211 bits <16> simm16; 212 213 let Inst{15-0} = simm16; 214 let Inst{22-16} = op; 215 let Inst{31-23} = 0x17f; // encoding 216 } 217 218 class SMRDe <bits<5> op, bits<1> imm> : Enc32 { 219 bits<7> sdst; 220 bits<7> sbase; 221 bits<8> offset; 222 223 let Inst{7-0} = offset; 224 let Inst{8} = imm; 225 let Inst{14-9} = sbase{6-1}; 226 let Inst{21-15} = sdst; 227 let Inst{26-22} = op; 228 let Inst{31-27} = 0x18; //encoding 229 } 230 231 class SMRD_IMMe_ci <bits<5> op> : Enc64 { 232 bits<7> sdst; 233 bits<7> sbase; 234 bits<32> offset; 235 236 let Inst{7-0} = 0xff; 237 let Inst{8} = 0; 238 let Inst{14-9} = sbase{6-1}; 239 let Inst{21-15} = sdst; 240 let Inst{26-22} = op; 241 let Inst{31-27} = 0x18; //encoding 242 let Inst{63-32} = offset; 243 } 244 245 let SchedRW = [WriteSALU] in { 246 class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> : 247 InstSI<outs, ins, asm, pattern> { 248 let mayLoad = 0; 249 let mayStore = 0; 250 let hasSideEffects = 0; 251 let isCodeGenOnly = 0; 252 let SALU = 1; 253 let SOP1 = 1; 254 } 255 256 class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> : 257 InstSI <outs, ins, asm, pattern> { 258 259 let mayLoad = 0; 260 let mayStore = 0; 261 let hasSideEffects = 0; 262 let isCodeGenOnly = 0; 263 let SALU = 1; 264 let SOP2 = 1; 265 266 let UseNamedOperandTable = 1; 267 } 268 269 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 270 InstSI<outs, ins, asm, pattern>, SOPCe <op> { 271 272 let mayLoad = 0; 273 let mayStore = 0; 274 let hasSideEffects = 0; 275 let SALU = 1; 276 let SOPC = 1; 277 let isCodeGenOnly = 0; 278 let Defs = [SCC]; 279 280 let UseNamedOperandTable = 1; 281 } 282 283 class SOPK <dag outs, dag ins, string asm, list<dag> pattern> : 284 InstSI <outs, ins , asm, pattern> { 285 286 let mayLoad = 0; 287 let mayStore = 0; 288 let hasSideEffects = 0; 289 let SALU = 1; 290 let SOPK = 1; 291 292 let UseNamedOperandTable = 1; 293 } 294 295 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> : 296 InstSI <(outs), ins, asm, pattern >, SOPPe <op> { 297 298 let mayLoad = 0; 299 let mayStore = 0; 300 let hasSideEffects = 0; 301 let SALU = 1; 302 let SOPP = 1; 303 304 let UseNamedOperandTable = 1; 305 } 306 307 } // let SchedRW = [WriteSALU] 308 309 class SMRD <dag outs, dag ins, string asm, list<dag> pattern> : 310 InstSI<outs, ins, asm, pattern> { 311 312 let LGKM_CNT = 1; 313 let SMRD = 1; 314 let mayStore = 0; 315 let mayLoad = 1; 316 let hasSideEffects = 0; 317 let UseNamedOperandTable = 1; 318 let SchedRW = [WriteSMEM]; 319 } 320 321 //===----------------------------------------------------------------------===// 322 // Vector ALU operations 323 //===----------------------------------------------------------------------===// 324 325 class VOP1e <bits<8> op> : Enc32 { 326 bits<8> vdst; 327 bits<9> src0; 328 329 let Inst{8-0} = src0; 330 let Inst{16-9} = op; 331 let Inst{24-17} = vdst; 332 let Inst{31-25} = 0x3f; //encoding 333 } 334 335 class VOP2e <bits<6> op> : Enc32 { 336 bits<8> vdst; 337 bits<9> src0; 338 bits<8> src1; 339 340 let Inst{8-0} = src0; 341 let Inst{16-9} = src1; 342 let Inst{24-17} = vdst; 343 let Inst{30-25} = op; 344 let Inst{31} = 0x0; //encoding 345 } 346 347 class VOP2_MADKe <bits<6> op> : Enc64 { 348 349 bits<8> vdst; 350 bits<9> src0; 351 bits<8> vsrc1; 352 bits<32> src2; 353 354 let Inst{8-0} = src0; 355 let Inst{16-9} = vsrc1; 356 let Inst{24-17} = vdst; 357 let Inst{30-25} = op; 358 let Inst{31} = 0x0; // encoding 359 let Inst{63-32} = src2; 360 } 361 362 class VOP3e <bits<9> op> : Enc64 { 363 bits<8> vdst; 364 bits<2> src0_modifiers; 365 bits<9> src0; 366 bits<2> src1_modifiers; 367 bits<9> src1; 368 bits<2> src2_modifiers; 369 bits<9> src2; 370 bits<1> clamp; 371 bits<2> omod; 372 373 let Inst{7-0} = vdst; 374 let Inst{8} = src0_modifiers{1}; 375 let Inst{9} = src1_modifiers{1}; 376 let Inst{10} = src2_modifiers{1}; 377 let Inst{11} = clamp; 378 let Inst{25-17} = op; 379 let Inst{31-26} = 0x34; //encoding 380 let Inst{40-32} = src0; 381 let Inst{49-41} = src1; 382 let Inst{58-50} = src2; 383 let Inst{60-59} = omod; 384 let Inst{61} = src0_modifiers{0}; 385 let Inst{62} = src1_modifiers{0}; 386 let Inst{63} = src2_modifiers{0}; 387 } 388 389 class VOP3be <bits<9> op> : Enc64 { 390 bits<8> vdst; 391 bits<2> src0_modifiers; 392 bits<9> src0; 393 bits<2> src1_modifiers; 394 bits<9> src1; 395 bits<2> src2_modifiers; 396 bits<9> src2; 397 bits<7> sdst; 398 bits<2> omod; 399 400 let Inst{7-0} = vdst; 401 let Inst{14-8} = sdst; 402 let Inst{25-17} = op; 403 let Inst{31-26} = 0x34; //encoding 404 let Inst{40-32} = src0; 405 let Inst{49-41} = src1; 406 let Inst{58-50} = src2; 407 let Inst{60-59} = omod; 408 let Inst{61} = src0_modifiers{0}; 409 let Inst{62} = src1_modifiers{0}; 410 let Inst{63} = src2_modifiers{0}; 411 } 412 413 class VOPCe <bits<8> op> : Enc32 { 414 bits<9> src0; 415 bits<8> vsrc1; 416 417 let Inst{8-0} = src0; 418 let Inst{16-9} = vsrc1; 419 let Inst{24-17} = op; 420 let Inst{31-25} = 0x3e; 421 } 422 423 class VINTRPe <bits<2> op> : Enc32 { 424 bits<8> vdst; 425 bits<8> vsrc; 426 bits<2> attrchan; 427 bits<6> attr; 428 429 let Inst{7-0} = vsrc; 430 let Inst{9-8} = attrchan; 431 let Inst{15-10} = attr; 432 let Inst{17-16} = op; 433 let Inst{25-18} = vdst; 434 let Inst{31-26} = 0x32; // encoding 435 } 436 437 class DSe <bits<8> op> : Enc64 { 438 bits<8> vdst; 439 bits<1> gds; 440 bits<8> addr; 441 bits<8> data0; 442 bits<8> data1; 443 bits<8> offset0; 444 bits<8> offset1; 445 446 let Inst{7-0} = offset0; 447 let Inst{15-8} = offset1; 448 let Inst{17} = gds; 449 let Inst{25-18} = op; 450 let Inst{31-26} = 0x36; //encoding 451 let Inst{39-32} = addr; 452 let Inst{47-40} = data0; 453 let Inst{55-48} = data1; 454 let Inst{63-56} = vdst; 455 } 456 457 class MUBUFe <bits<7> op> : Enc64 { 458 bits<12> offset; 459 bits<1> offen; 460 bits<1> idxen; 461 bits<1> glc; 462 bits<1> addr64; 463 bits<1> lds; 464 bits<8> vaddr; 465 bits<8> vdata; 466 bits<7> srsrc; 467 bits<1> slc; 468 bits<1> tfe; 469 bits<8> soffset; 470 471 let Inst{11-0} = offset; 472 let Inst{12} = offen; 473 let Inst{13} = idxen; 474 let Inst{14} = glc; 475 let Inst{15} = addr64; 476 let Inst{16} = lds; 477 let Inst{24-18} = op; 478 let Inst{31-26} = 0x38; //encoding 479 let Inst{39-32} = vaddr; 480 let Inst{47-40} = vdata; 481 let Inst{52-48} = srsrc{6-2}; 482 let Inst{54} = slc; 483 let Inst{55} = tfe; 484 let Inst{63-56} = soffset; 485 } 486 487 class MTBUFe <bits<3> op> : Enc64 { 488 bits<8> vdata; 489 bits<12> offset; 490 bits<1> offen; 491 bits<1> idxen; 492 bits<1> glc; 493 bits<1> addr64; 494 bits<4> dfmt; 495 bits<3> nfmt; 496 bits<8> vaddr; 497 bits<7> srsrc; 498 bits<1> slc; 499 bits<1> tfe; 500 bits<8> soffset; 501 502 let Inst{11-0} = offset; 503 let Inst{12} = offen; 504 let Inst{13} = idxen; 505 let Inst{14} = glc; 506 let Inst{15} = addr64; 507 let Inst{18-16} = op; 508 let Inst{22-19} = dfmt; 509 let Inst{25-23} = nfmt; 510 let Inst{31-26} = 0x3a; //encoding 511 let Inst{39-32} = vaddr; 512 let Inst{47-40} = vdata; 513 let Inst{52-48} = srsrc{6-2}; 514 let Inst{54} = slc; 515 let Inst{55} = tfe; 516 let Inst{63-56} = soffset; 517 } 518 519 class MIMGe <bits<7> op> : Enc64 { 520 bits<8> vdata; 521 bits<4> dmask; 522 bits<1> unorm; 523 bits<1> glc; 524 bits<1> da; 525 bits<1> r128; 526 bits<1> tfe; 527 bits<1> lwe; 528 bits<1> slc; 529 bits<8> vaddr; 530 bits<7> srsrc; 531 bits<7> ssamp; 532 533 let Inst{11-8} = dmask; 534 let Inst{12} = unorm; 535 let Inst{13} = glc; 536 let Inst{14} = da; 537 let Inst{15} = r128; 538 let Inst{16} = tfe; 539 let Inst{17} = lwe; 540 let Inst{24-18} = op; 541 let Inst{25} = slc; 542 let Inst{31-26} = 0x3c; 543 let Inst{39-32} = vaddr; 544 let Inst{47-40} = vdata; 545 let Inst{52-48} = srsrc{6-2}; 546 let Inst{57-53} = ssamp{6-2}; 547 } 548 549 class FLATe<bits<7> op> : Enc64 { 550 bits<8> addr; 551 bits<8> data; 552 bits<8> vdst; 553 bits<1> slc; 554 bits<1> glc; 555 bits<1> tfe; 556 557 // 15-0 is reserved. 558 let Inst{16} = glc; 559 let Inst{17} = slc; 560 let Inst{24-18} = op; 561 let Inst{31-26} = 0x37; // Encoding. 562 let Inst{39-32} = addr; 563 let Inst{47-40} = data; 564 // 54-48 is reserved. 565 let Inst{55} = tfe; 566 let Inst{63-56} = vdst; 567 } 568 569 class EXPe : Enc64 { 570 bits<4> en; 571 bits<6> tgt; 572 bits<1> compr; 573 bits<1> done; 574 bits<1> vm; 575 bits<8> vsrc0; 576 bits<8> vsrc1; 577 bits<8> vsrc2; 578 bits<8> vsrc3; 579 580 let Inst{3-0} = en; 581 let Inst{9-4} = tgt; 582 let Inst{10} = compr; 583 let Inst{11} = done; 584 let Inst{12} = vm; 585 let Inst{31-26} = 0x3e; 586 let Inst{39-32} = vsrc0; 587 let Inst{47-40} = vsrc1; 588 let Inst{55-48} = vsrc2; 589 let Inst{63-56} = vsrc3; 590 } 591 592 let Uses = [EXEC] in { 593 594 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : 595 VOP1Common <outs, ins, asm, pattern>, 596 VOP1e<op> { 597 let isCodeGenOnly = 0; 598 } 599 600 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> : 601 VOP2Common <outs, ins, asm, pattern>, VOP2e<op> { 602 let isCodeGenOnly = 0; 603 } 604 605 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> : 606 VOPCCommon <ins, asm, pattern>, VOPCe <op>; 607 608 class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> : 609 InstSI <outs, ins, asm, pattern> { 610 let mayLoad = 1; 611 let mayStore = 0; 612 let hasSideEffects = 0; 613 } 614 615 } // End Uses = [EXEC] 616 617 //===----------------------------------------------------------------------===// 618 // Vector I/O operations 619 //===----------------------------------------------------------------------===// 620 621 class DS <dag outs, dag ins, string asm, list<dag> pattern> : 622 InstSI <outs, ins, asm, pattern> { 623 624 let LGKM_CNT = 1; 625 let DS = 1; 626 let UseNamedOperandTable = 1; 627 let Uses = [M0, EXEC]; 628 629 // Most instruction load and store data, so set this as the default. 630 let mayLoad = 1; 631 let mayStore = 1; 632 633 let hasSideEffects = 0; 634 let AsmMatchConverter = "cvtDS"; 635 let SchedRW = [WriteLDS]; 636 } 637 638 class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> : 639 InstSI<outs, ins, asm, pattern> { 640 641 let VM_CNT = 1; 642 let EXP_CNT = 1; 643 let MUBUF = 1; 644 let Uses = [EXEC]; 645 646 let hasSideEffects = 0; 647 let UseNamedOperandTable = 1; 648 let AsmMatchConverter = "cvtMubuf"; 649 let SchedRW = [WriteVMEM]; 650 } 651 652 class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> : 653 InstSI<outs, ins, asm, pattern> { 654 655 let VM_CNT = 1; 656 let EXP_CNT = 1; 657 let MTBUF = 1; 658 let Uses = [EXEC]; 659 660 let hasSideEffects = 0; 661 let UseNamedOperandTable = 1; 662 let SchedRW = [WriteVMEM]; 663 } 664 665 class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 666 InstSI<outs, ins, asm, pattern>, FLATe <op> { 667 let FLAT = 1; 668 // Internally, FLAT instruction are executed as both an LDS and a 669 // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT 670 // and are not considered done until both have been decremented. 671 let VM_CNT = 1; 672 let LGKM_CNT = 1; 673 674 let Uses = [EXEC, FLAT_SCR]; // M0 675 676 let UseNamedOperandTable = 1; 677 let hasSideEffects = 0; 678 let AsmMatchConverter = "cvtFlat"; 679 let SchedRW = [WriteVMEM]; 680 } 681 682 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 683 InstSI <outs, ins, asm, pattern>, MIMGe <op> { 684 685 let VM_CNT = 1; 686 let EXP_CNT = 1; 687 let MIMG = 1; 688 let Uses = [EXEC]; 689 690 let hasSideEffects = 0; // XXX ???? 691 } 692
